A counter circuit built from flip-flops counts input pulses and displays the accumulated total in binary on its output lines. Each flip-flop in the chain stores one bit of the count and toggles at half the rate of the previous stage — flip-flop 0 toggles every pulse, flip-flop 1 every two pulses, flip-flop 2 every four pulses, and so on. Two flip-flops build a 2-bit counter (0–3), four flip-flops build a 4-bit counter (0–15), and chaining more stages extends the count range arbitrarily. Counter circuits are the foundation of digital timers, event counters, frequency dividers, address generators, and sequencing circuits throughout electronics.
Introduction: Teaching Circuits to Count
The gate circuits covered in previous articles are all combinational — they respond instantly to their current inputs, with no memory of the past. Apply the same inputs and you always get the same outputs. Remove the inputs and the circuit knows nothing. These circuits make decisions and perform calculations but cannot track anything over time.
Counting requires time. To count to ten, you must remember you have seen one, then two, then three… the count accumulates with each event. Memory is essential. And memory in digital circuits means flip-flops — the bistable elements that hold a state indefinitely until deliberately changed by a clock edge.
When flip-flops are connected so that each one’s output drives the next one’s clock input, something elegant emerges: the chain automatically counts in binary. The first flip-flop toggles on every input pulse, producing a square wave at half the input frequency. The second flip-flop sees this square wave as its clock — it toggles every time the first flip-flop goes from HIGH to LOW, producing a square wave at one quarter the input frequency. The third flip-flop toggles at one eighth the rate. Reading all the flip-flop outputs together gives a binary number that increments by one with each input pulse. The circuit is counting.
This article builds counter circuits from the ground up, starting from a single toggle flip-flop, progressing through 2-bit and 4-bit ripple counters, explaining the timing and propagation delay that limits ripple counters, introducing synchronous counters that overcome those limits, covering the 74HC163 synchronous counter IC, and working through five complete practical designs — from a breadboard pulse counter with LED display through a modulo-N timer and a frequency divider for audio tones.
The Toggle Flip-Flop: The Atom of Counting
D Flip-Flop Wired as Toggle
A D flip-flop captures whatever is on its D input at the rising clock edge. If we connect Q̄ back to D, then:
- When Q = 0: D = Q̄ = 1. At the next rising clock edge, Q captures 1 → Q becomes 1.
- When Q = 1: D = Q̄ = 0. At the next rising clock edge, Q captures 0 → Q becomes 0.
The output toggles — changes to its opposite — on every rising clock edge. This is a T (toggle) flip-flop with T permanently wired to 1.
The divide-by-2 behavior:
CLK: ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
Q: ───┐ ┌───┐ ┌───┐ ┌───┐ ┌──
└───┘ └───┘ └───┘ └───┘Q completes one full HIGH-LOW cycle for every two CLK cycles. Output frequency = CLK frequency ÷ 2. The flip-flop is counting modulo 2 — cycling through {0, 1, 0, 1, …} — and the output Q reads the current count.
Why This Is Counting
After 0 pulses: Q = 0 (count = 0) After 1 pulse: Q = 1 (count = 1) After 2 pulses: Q = 0 (count = 0, wrapped back to start)
One flip-flop counts from 0 to 1 — a 1-bit binary counter. To count higher, add more flip-flops.
Building a 2-Bit Ripple Counter
The Two-Stage Chain
Connect the Q output of the first flip-flop to the CLK input of the second flip-flop. Both flip-flops are wired as toggles (Q̄ → D):
Input CLK → [FF0] → Q0 → CLK of [FF1] → Q1
D0 = Q̄0 D1 = Q̄1Critical detail — falling edge triggering: When using positive-edge-triggered D flip-flops (which trigger on CLK rising edge), connecting Q0 to CLK1 means FF1 triggers on the RISING edge of Q0. But Q0 rises when the count goes from 0→1, 2→3, etc. — not the transitions that create correct binary counting. We want FF1 to advance when Q0 falls (transitions 1→0, i.e., at counts 1→2 and 3→4).
Solution 1: Use Q̄0 as the clock input to FF1. Q̄0 rises exactly when Q0 falls. This is the standard approach.
Solution 2: Use negative-edge-triggered flip-flops (trigger on falling edge). Many counter ICs use this internally.
Solution 3: In practice with 74HC74 positive-edge-triggered flip-flops, connect Q̄0 to CLK1. Q̄0’s rising edge coincides with Q0’s falling edge — correct triggering.
The Count Sequence
With Q̄0 → CLK1 connection, trace the behavior:
Starting state: Q1Q0 = 00 (count = 0)
| Pulse | Q1 | Q0 | Count (Q1Q0) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 2 | 1 | 0 | 2 |
| 3 | 1 | 1 | 3 |
| 4 | 0 | 0 | 0 (wraps) |
Reading Q1Q0 as a 2-bit binary number gives the exact count. The circuit counts 0, 1, 2, 3, 0, 1, 2, 3 — modulo 4.
Timing diagram:
CLK: ─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘
Q0: ───┐ ┌───┐ ┌───┐ ┌───┐ ┌──
└───┘ └───┘ └───┘ └───┘
Q̄0: ─┐ ┌───┐ ┌───┐ ┌───┐ ┌──
└───┘ └───┘ └───┘ └───┘
Q1: ───────┐ ┌───────┐ ┌──
└───────┘ └───────┘
Q1 rises when Q̄0 rises (i.e., when Q0 falls — pulse 2 and 4). Q1 falls when Q̄0 rises again — pulse 4 and 8. Perfect binary counting.
Wiring the 2-Bit Counter with 74HC74
The 74HC74 contains two positive-edge-triggered D flip-flops with independent CLK, D, PRE̅, and CLR̅ inputs.
74HC74 pinout:
Pin 1: CLR̅1 (active-LOW asynchronous reset, flip-flop 1)
Pin 2: D1
Pin 3: CLK1
Pin 4: PRE̅1 (active-LOW asynchronous preset)
Pin 5: Q1
Pin 6: Q̄1
Pin 7: GND
Pin 8: Q̄2
Pin 9: Q2
Pin 10: PRE̅2
Pin 11: CLK2
Pin 12: D2
Pin 13: CLR̅2
Pin 14: VCCComplete 2-bit counter wiring:
74HC74 connections:
Pin 2 (D1) ← Pin 6 (Q̄1) [FF1: D=Q̄, wired as toggle]
Pin 3 (CLK1) ← Input pulse
Pin 4 (PRE̅1) → VCC [Not using preset]
Pin 1 (CLR̅1) → RESET button (or VCC if no reset needed)
Pin 5 (Q1) → LED0 (bit 0 output) and Pin 8 (Q̄2) [Q0 → Q̄1 used for FF2 clock]
Pin 6 (Q̄1) → Pin 11 (CLK2) [Q̄0 clocks FF2 on rising edge = Q0 falling edge]
Pin 12 (D2) ← Pin 8 (Q̄2) [FF2: D=Q̄, wired as toggle]
Pin 10 (PRE̅2) → VCC
Pin 13 (CLR̅2) → RESET (same as CLR̅1)
Pin 9 (Q2) → LED1 (bit 1 output)
Pin 14 → VCC (5V)
Pin 7 → GND
100nF ceramic capacitor between VCC (pin 14) and GND (pin 7)Input pulse switch: Connect a push button between the CLK1 input and GND. Pull CLK1 to VCC through a 10kΩ resistor. Each button press pulls CLK1 LOW briefly; releasing it returns CLK1 HIGH, creating a rising edge that advances FF1.
Note: a mechanical push button bounces — each physical press may create 5–50 rising edges. For proper counting, debounce the button first. Options:
- RC filter (10kΩ + 100nF) on the button output, followed by a Schmitt trigger (74HC14 inverter)
- NAND SR latch debounce circuit (two gates of 74HC00) as covered in Article 78
- Slow down pressing: at counting rates below ~10 pulses/second, most button bounces are within the first 10ms and produce extra counts
For demonstration purposes at slow press rates, the bare button may work acceptably. For reliable counting at any speed, add debounce.
Reset wiring: Connect CLR̅1 and CLR̅2 together to a push button pull-up arrangement: pull CLR̅ HIGH through 10kΩ, button shorts to GND. Pressing RESET pulls both CLR̅ pins LOW simultaneously, immediately resetting Q1=Q2=0 (asynchronous reset — does not need a clock edge).
Extending to a 4-Bit Counter
Adding More Stages
The same principle extends to any number of bits. A 4-bit counter adds FF3 and FF4, each clocked by the Q̄ of the previous stage:
CLK → [FF0] → Q̄0 → [FF1] → Q̄1 → [FF2] → Q̄2 → [FF3]
Q0 Q1 Q2 Q3Count sequence: 0000 through 1111 (0 through 15 in decimal), then wraps back to 0000. This is a modulo-16 (divide-by-16) counter.
Two 74HC74 ICs provide the four flip-flops:
- IC1 provides FF0 (using flip-flop 1 of the 74HC74) and FF1 (flip-flop 2)
- IC2 provides FF2 and FF3
Wiring additions for IC2:
IC2 74HC74:
Pin 3 (CLK1) ← IC1 pin 8 (Q̄2) [Q̄1 from FF1 clocks FF2]
Pin 2 (D1) ← Pin 6 (Q̄1 of IC2) [FF2 wired as toggle]
Pin 5 (Q1 of IC2) → LED2 (bit 2 output)
Pin 6 (Q̄1 of IC2) → Pin 11 (CLK2 of IC2)
Pin 11 (CLK2) ← Pin 6 (Q̄1 of IC2) [Q̄2 clocks FF3]
Pin 12 (D2) ← Pin 8 (Q̄2 of IC2) [FF3 wired as toggle]
Pin 9 (Q2 of IC2) → LED3 (bit 3 output)
All PRE̅ pins → VCC
All CLR̅ pins → RESET line (shared with IC1)LED display: Four LEDs (LED0–LED3), each with a 470Ω series resistor to GND. When Q outputs are HIGH (5V): LED current = (5V − 2V) / 470Ω ≈ 6.4mA — safely within 74HC74 output drive.
Reading the four LEDs left to right (LED3 = MSB, LED0 = LSB) gives the count in binary. After pressing the input button 10 times: LED display shows 1010 (binary for decimal 10).
The Complete 4-Bit Counter Component List
- 2× 74HC74 dual D flip-flop
- 4× LEDs (red or green)
- 4× 470Ω resistors (LED current limiting)
- 1× push button (count input)
- 1× push button (reset)
- 2× 10kΩ resistors (pull-ups for buttons)
- 2× 100nF ceramic capacitors (decoupling, one per IC)
- 5V power supply
- Breadboard and jumper wires
Understanding Ripple Delay
The Problem with Chained Clocking
The counter described above is called a ripple counter or asynchronous counter because the state changes propagate (ripple) through the chain one flip-flop at a time, each stage delayed from the previous by one propagation delay (t_pCLK-Q).
When the count transitions from 0111 (7) to 1000 (8):
- CLK rising edge: FF0 toggles. Q0: 1→0. Delay: t_pCLK-Q ≈ 14ns.
- Q̄0 rising edge: FF1 toggles. Q1: 1→0. Delay: another 14ns.
- Q̄1 rising edge: FF2 toggles. Q2: 1→0. Delay: another 14ns.
- Q̄2 rising edge: FF3 toggles. Q3: 0→1. Delay: another 14ns.
Total time from CLK edge to valid Q3: 4 × 14ns = 56ns.
During those 56ns, the counter output is wrong — it passes through transient states:
0111 → 0110 → 0100 → 0000 → 1000These intermediate states exist for real — they appear on the output pins and will trigger any decoding logic that is watching.
Consequences of Ripple Delay
Speed limit: The input clock period must be longer than the total ripple delay. For a 4-bit 74HC74 ripple counter:
f_max = 1 / (N × t_pCLK-Q) = 1 / (4 × 14ns) = 17.9MHz (theoretical)With a 2× safety margin, practical maximum: ~8MHz. This is adequate for many applications but insufficient for systems clocked at tens or hundreds of MHz.
Glitches in decoded outputs: If you use AND/NAND gates to decode a specific count (e.g., detect count = 8 for a timer), those gates may falsely trigger during the transient 0000 state. Decode logic downstream of a ripple counter needs careful timing analysis.
Not suitable for synchronous systems: Connecting ripple counter outputs to logic clocked by the same input clock is dangerous — different bits of the count are valid at different times, violating the synchronous design principle that all flip-flops see stable inputs before their clock edge.
When Ripple Counters Are Fine
Despite their limitations, ripple counters work well for:
- Low-speed counting (input rates far below the ripple delay limit)
- Frequency division (dividing a clock by a power of 2 — only the final flip-flop output is used, which is always stable)
- Display applications where brief transients are invisible to the human eye or display refresh rate
- Learning and demonstration circuits where timing precision is not critical
Synchronous Counters: All Flip-Flops Together
The Synchronous Solution
A synchronous counter connects all flip-flops to the same clock. Instead of each stage clocking the next, combinational logic computes when each stage should toggle, and the clock simultaneously updates all stages.
The key insight: flip-flop N should toggle when ALL lower flip-flops (0 through N-1) are HIGH. This is the carry condition — only when all lower bits are 1 does incrementing by 1 cause flip-flop N to change.
Next-state logic for a 4-bit synchronous up-counter:
D0 = Q̄0 (Q0 always toggles)
D1 = Q1 ⊕ Q0 (Q1 toggles when Q0 = 1)
D2 = Q2 ⊕ (Q0 · Q1) (Q2 toggles when Q0 = 1 AND Q1 = 1)
D3 = Q3 ⊕ (Q0 · Q1 · Q2) (Q3 toggles when Q0 = Q1 = Q2 = 1)
All flip-flops share one clock. On each rising clock edge, all D inputs are captured simultaneously. No ripple, no transient states.
Gate Implementation
Gate 1 (NOT): Q0 → Q̄0 → D0
Gate 2 (AND): Q0, Q1 → CARRY_01
Gate 3 (AND, 3-input): Q0, Q1, Q2 → CARRY_012
Gate 4 (XOR): Q1, Q0 → D1
Gate 5 (XOR): Q2, CARRY_01 → D2
Gate 6 (XOR): Q3, CARRY_012 → D3ICs: 2× 74HC74 (flip-flops) + 74HC86 (XOR for D1, D2, D3) + 74HC08 (AND for carry signals) + 74HC04 (NOT for D0).
Verification
Starting from Q3Q2Q1Q0 = 0111 (count = 7), verify transition to 1000:
D0 = Q̄0 = 0̄ = 1... wait, Q0=1 so D0 = Q̄0 = 0 ✓ (Q0 will go from 1→0)
CARRY_01 = Q0·Q1 = 1·1 = 1
D1 = Q1 ⊕ Q0 = 1 ⊕ 1 = 0 ✓ (Q1 goes from 1→0)
CARRY_012 = Q0·Q1·Q2 = 1·1·1 = 1
D2 = Q2 ⊕ CARRY_01 = 1 ⊕ 1 = 0 ✓ (Q2 goes from 1→0)
D3 = Q3 ⊕ CARRY_012 = 0 ⊕ 1 = 1 ✓ (Q3 goes from 0→1)Next state: Q3Q2Q1Q0 = 1000 (count = 8) ✓ — all transitions happen simultaneously on the clock edge, no ripple.
The 74HC163: Synchronous 4-Bit Counter IC
For practical designs, the 74HC163 integrates a complete synchronous 4-bit binary counter with parallel load, enable, and synchronous reset in a single 16-pin IC.
Pin Assignments
| Pin | Name | Function |
|---|---|---|
| 1 | CLR̅ | Synchronous clear (active-LOW: resets to 0000 on next CLK↑) |
| 2 | CLK | Clock input (positive-edge triggered) |
| 3 | A | Parallel load input, bit 0 |
| 4 | B | Parallel load input, bit 1 |
| 5 | C | Parallel load input, bit 2 |
| 6 | D | Parallel load input, bit 3 |
| 7 | CEP | Count Enable Parallel (HIGH = count enabled) |
| 8 | GND | Ground |
| 9 | CET | Count Enable Trickle (HIGH = count enabled, also gates TC output) |
| 10 | TC | Terminal Count output (HIGH when count = 15 AND CET = 1) |
| 11 | QD | Q output, bit 3 (MSB) |
| 12 | QC | Q output, bit 2 |
| 13 | QB | Q output, bit 1 |
| 14 | QA | Q output, bit 0 (LSB) |
| 15 | PE̅ | Parallel Enable (active-LOW: loads A-D into counter on next CLK↑) |
| 16 | VCC | Supply |
Operating Modes
| CLR̅ | PE̅ | CEP | CET | Operation |
|---|---|---|---|---|
| 0 | X | X | X | Synchronous reset to 0000 on CLK↑ |
| 1 | 0 | X | X | Synchronous parallel load (QA-QD ← A-D) on CLK↑ |
| 1 | 1 | 1 | 1 | Count (increment) on CLK↑ |
| 1 | 1 | 0 | X | Hold (no counting) |
| 1 | 1 | X | 0 | Hold (TC forced LOW) |
For basic free-running 0–15 counter: tie CLR̅, CEP, and CET HIGH; tie PE̅ HIGH; ignore A-D inputs. Connect CLK to clock source. QA-QD are the count outputs. TC goes HIGH when count = 15.
Cascading Two 74HC163s for 8-Bit Counting
Connect TC of the lower counter (bits 3-0) to CET of the upper counter (bits 7-4). Both counters share the same CLK:
74HC163 LOW: 74HC163 HIGH:
CLR̅ → VCC CLR̅ → VCC
CEP → VCC CEP → VCC
CET → VCC CET ← TC of LOW
PE̅ → VCC PE̅ → VCC
CLK ← system clock CLK ← same system clock
TC → CET of HIGH
QA-QD → bits 3-0 QA-QD → bits 7-4TC of LOW goes HIGH when LOW counter = 15 (1111). This enables the HIGH counter to increment on the next clock edge. TC of HIGH goes HIGH when HIGH = 15 AND CET (= TC_LOW) = 1 — only when both counters are at 15 (full count = 255). Fully synchronous — no ripple.
Building Modulo-N Counters
A modulo-N counter counts from 0 to N-1, then resets to 0. Used for decade counting (N=10), seconds/minutes (N=60), and any application requiring a non-power-of-2 count range.
Method: Synchronous Reset at Count N
Using the 74HC163’s synchronous CLR̅:
Step 1: Decode count = N using NAND gate(s). Step 2: Connect decoder output to CLR̅.
When the counter reaches N, CLR̅ goes LOW, and on the NEXT clock edge the counter resets to 0. The counter reaches N for exactly one clock cycle then immediately resets — the sequence is 0, 1, 2, …, N-1, 0, 1, …
Example: Modulo-10 counter (decade counter)
Count 10 = 1010 binary (QD=1, QC=0, QB=1, QA=0).
Decode: CLR̅ = NAND(QD, QB)
- When count = 10: QD=1, QB=1 → NAND(1,1) = 0 → CLR̅ = LOW ✓
- All other counts: at least one of QD or QB is 0 → NAND output = 1 → CLR̅ = HIGH ✓
Within a modulo-10 counter, count never reaches 11–15 (resets before getting there), so no other combination of QD=1 and QB=1 occurs except at count 10. The NAND(QD, QB) detection is unambiguous.
Gate: One 74HC00 NAND gate. Together with a 74HC163, this creates a complete decade (0–9) counter.
Complete modulo-10 counter:
74HC163:
CLR̅ ← NAND(QD, QB) [one gate from 74HC00]
CEP = CET = VCC
PE̅ = VCC
CLK ← clock input
QA-QD → outputsOther Useful Modulo Values
| N | Binary representation | NAND decode |
|---|---|---|
| 6 | 0110 (QC=1, QB=1) | NAND(QC, QB) |
| 10 | 1010 (QD=1, QB=1) | NAND(QD, QB) |
| 12 | 1100 (QD=1, QC=1) | NAND(QD, QC) |
| 16 | Uses TC output naturally | (no decode needed) |
| 60 | Two cascaded counters (modulo-6 × modulo-10) | See below |
Modulo-60 counter (for seconds/minutes display):
- Stage 1 (units of seconds/minutes): modulo-10 counter (74HC163 + NAND)
- Stage 2 (tens of seconds/minutes): modulo-6 counter, clocked by TC of Stage 1
For Stage 2 modulo-6: count 6 = 0110 (QC=1, QB=1). Decode: CLR̅ = NAND(QC, QB).
Together: 2× 74HC163 + 2× NAND gates = a complete modulo-60 counter for clock seconds/minutes.
Complete Design Examples
Design Example 1: 4-Bit Breadboard Counter with LED Display
Application: Hands-on learning circuit. Count button presses and display the count (0–15) in binary on four LEDs. Manual reset button. Built entirely on a breadboard.
Components:
- 2× 74HC74 (dual D flip-flop)
- 4× red LEDs
- 4× 470Ω resistors
- 2× 10kΩ pull-up resistors (for buttons)
- 2× push buttons (COUNT, RESET)
- 1× 10kΩ resistor + 1× 100nF capacitor (RC debounce for COUNT button)
- 1× 74HC14 (Schmitt trigger hex inverter — for debouncing count input)
- 2× 100nF ceramic capacitors (decoupling)
- Breadboard, jumper wires, 5V supply
Button debounce using RC + Schmitt trigger:
VCC ─[10kΩ]─┬─── 74HC14 pin 1 (input)
│ │
COUNT [100nF]
button │
│ GND
GND
74HC14 pin 2 (output) → 74HC14 pin 3 (second inverter)
74HC14 pin 4 (output) → CLK1 of FF0 (74HC74 pin 3)Two inverters in series: double inversion = non-inverting buffer. The RC slows the button signal, Schmitt trigger cleans it up, double inversion restores correct polarity.
Wiring summary:
IC1 (74HC74):
FF0 (left flip-flop):
CLK1 (pin 3) ← debounced COUNT button
D1 (pin 2) ← Q̄1 (pin 6) [toggle]
PRE̅1 (pin 4) → VCC
CLR̅1 (pin 1) → RESET button pull-up
Q1 (pin 5) → LED0 (470Ω → GND) and Q̄2 (pin 8 of same IC)
FF1 (right flip-flop):
CLK2 (pin 11) ← Q̄1 (pin 6) [Q̄0 clocks FF1]
D2 (pin 12) ← Q̄2 (pin 8) [toggle]
PRE̅2 (pin 10) → VCC
CLR̅2 (pin 13) → RESET button pull-up (shared with CLR̅1)
Q2 (pin 9) → LED1 (470Ω → GND)
IC2 (74HC74):
FF2:
CLK1 (pin 3) ← Q̄2 (IC1 pin 8)
D1 (pin 2) ← Q̄1 (IC2 pin 6)
CLR̅1 (pin 1) → RESET
Q1 (pin 5) → LED2 (470Ω → GND)
FF3:
CLK2 (pin 11) ← Q̄1 (IC2 pin 6)
D2 (pin 12) ← Q̄2 (IC2 pin 8)
CLR̅2 (pin 13) → RESET
Q2 (pin 9) → LED3 (470Ω → GND)Testing procedure:
- Power up — all LEDs should be off (count = 0000)
- Press COUNT once — LED0 lights (count = 0001 = 1)
- Press COUNT again — LED0 off, LED1 on (count = 0010 = 2)
- Count to 7 (LED2, LED1, LED0 all on = 0111)
- Count to 8 — LED3 on, others off (1000 = 8)
- Count to 15 — all LEDs on (1111 = 15)
- Count once more — all LEDs off (wraps to 0000 = 0)
- Press RESET — all LEDs off immediately (asynchronous reset)
Design Example 2: Decade Counter with 7-Segment Display
Application: Count from 0 to 9, display on a 7-segment LED display. Reset automatically at 10.
Components:
- 1× 74HC163 (synchronous 4-bit counter)
- 1× 74HC00 (NAND gate for modulo-10 decode)
- 1× 74HC4511 (BCD to 7-segment decoder/driver)
- 1× common-cathode 7-segment LED display
- 7× 330Ω resistors (segment current limiting)
- 100nF decoupling capacitors
- Clock source (555 timer, crystal oscillator, or MCU PWM)
74HC4511 connections:
- A(pin 7) ← QA of 74HC163 (pin 14)
- B(pin 1) ← QB (pin 13)
- C(pin 2) ← QC (pin 12)
- D(pin 6) ← QD (pin 11)
- LT̅(pin 3) → VCC (lamp test off)
- BL̅(pin 4) → VCC (blanking off)
- LE(pin 5) → GND (latch enable off — display always follows input)
- VCC(pin 16) → 5V, GND(pin 8) → GND
- Outputs a-g → 330Ω → 7-segment display segments a-g
Modulo-10 decode:
- 74HC00 gate: inputs = QD(pin 11) and QB(pin 13) of 74HC163
- Output → CLR̅(pin 1) of 74HC163
Clock source using 555 astable: For ~1Hz clock (visible counting): R1 = 10kΩ, R2 = 68kΩ, C = 10µF.
f = 1.44 / ((R1 + 2×R2) × C) = 1.44 / (146,000 × 10×10⁻⁶) ≈ 0.986Hz ≈ 1HzThe display counts 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1… once per second.
Power-on reset: Add a 10µF capacitor from CLR̅ to GND with a 10kΩ pull-up to VCC. On power-up, the capacitor holds CLR̅ LOW for approximately 100ms (R×C = 10kΩ × 10µF = 100ms), resetting the counter to 0000 before the clock starts advancing it.
Design Example 3: Frequency Divider for Audio Tones
Application: Divide a master 4MHz crystal oscillator down to musical note frequencies for an electronic organ or tone generator. Middle C = 261.63Hz.
Required division: 4,000,000 / 261.63 ≈ 15,290
This requires a modulo-15,290 counter — beyond a single 74HC163 (max modulo 16). Use two cascaded 74HC163s (modulo up to 256) plus additional stages, or use the parallel-load technique:
Parallel load method: Preset the counter to (65,536 – 15,290) = 50,246 and count up to 65,535. When TC fires (count = 65,535), reload 50,246 on the next clock edge. The count cycles through 15,290 states before each TC pulse.
For two cascaded 74HC163s (max 256 states), a 15,290 division requires four cascaded counters (max 65,536 states):
Four cascaded 74HC163s:
- IC1 (bits 3-0): preset value lower nibble of 50,246 = 50,246 mod 16 = 6 (0110)
- IC2 (bits 7-4): (50,246 >> 4) mod 16 = 3147 mod 16 = 11 (1011)
- IC3 (bits 11-8): (50,246 >> 8) mod 16 = 196 mod 16 = 4 (0100)
- IC4 (bits 15-12): (50,246 >> 12) = 12 (1100)
50,246 in 16-bit binary: 1100 0100 1011 0110 — confirmed.
TC chaining: IC1-TC → IC2-CET, IC2-TC → IC3-CET, IC3-TC → IC4-CET. IC4-TC → all four PE̅ inputs (through one NOT gate from 74HC04, since PE̅ is active-LOW and TC is active-HIGH).
When IC4-TC fires: NOT(TC) = LOW → PE̅ = LOW → all four counters parallel-load their preset values on the next clock edge → cycle repeats.
Output: IC4-TC is a pulse at 4MHz / 15,290 = 261.6Hz ≈ Middle C.
Other notes: Change the preset value for different notes. For A4 (440Hz): 4,000,000 / 440 = 9,090 pulses per cycle → preset = 65,536 – 9,090 = 56,446.
Design Example 4: 60-Second Timer with Display
Application: Count elapsed seconds from 0 to 59, display on two 7-segment displays (tens and units). Push button START/STOP. Wraps after 59.
Architecture:
1Hz clock → Counter UNITS (modulo-10) → carry → Counter TENS (modulo-6) → displayCounter UNITS (modulo-10):
- 74HC163 with NAND(QD, QB) → CLR̅ (resets at 10)
- QA-QD → 74HC4511 → units 7-segment display
Carry signal for tens counter: When units counter reaches 9 and advances to 10 (triggering reset), TC fires momentarily. But TC of the standard 74HC163 fires at count 15, not 9 — not directly usable here.
Alternative: generate carry from count = 9 detection:
CARRY_UNITS = QD · QA [count 9 = 1001: both QD and QA are HIGH]This signal goes HIGH for one clock cycle when units = 9. Use as clock for tens counter.
Wait — we need a pulse on the transition from 9 to 0, not a level while count = 9. The rising edge of the next clock (which resets units to 0) can serve as the tens clock. Or more simply: clock the tens counter with the CLK signal gated by CARRY_UNITS:
TENS_CLK = CLK · CARRY_UNITSWhen units = 9 (CARRY_UNITS = HIGH): the next CLK pulse passes through to the tens counter. When units ≠ 9 (CARRY_UNITS = LOW): CLK is blocked from tens counter.
Counter TENS (modulo-6):
- 74HC163 clocked by TENS_CLK (gated CLK)
- CLR̅ = NAND(QC, QB) [count 6 = 0110: resets at 6]
- QA-QD → 74HC4511 → tens 7-segment display
START/STOP:
- STOP/RUN flip-flop (D flip-flop from 74HC74) toggles on START/STOP button press
- RUN signal gates the 1Hz clock: GATED_CLK = 1Hz AND RUN
- RESET button → CLR̅ of both counters simultaneously
1Hz clock generation: Use a crystal oscillator module (32,768Hz) divided by 32,768 (15 flip-flops in chain, or use a dedicated divider IC like the CD4060 which includes 14 binary divider stages).
Alternatively, the 555 timer in astable mode: R1=1kΩ, R2=360kΩ, C=2.2µF gives approximately 0.91Hz — close enough for a non-precision timer (adjust R2 for exact 1Hz).
Complete IC count: 2× 74HC163 (counters), 2× 74HC4511 (display decoders), 2× 74HC00 (NAND for decode and carry gate), 74HC08 (AND for clock gating), 74HC74 (START/STOP flip-flop), 555 timer (clock). About 8 ICs total — a manageable real-world design.
Design Example 5: Pulse Counter with Serial Readout
Application: Count pulses from an industrial sensor (0–255 per measurement cycle). After the measurement window, a microcontroller reads the 8-bit count via SPI and resets the counter for the next cycle. No display — count is processed digitally.
Architecture: Two cascaded 74HC163s (8-bit count, 0–255) → microcontroller reads QA-QD of both ICs directly as parallel bits.
MCU interface:
- 8 GPIO inputs on the MCU read QA-QD of IC1 and IC2 directly
- RESET signal from MCU CLR̅ both counters after reading
- COUNT_ENABLE from MCU → CEP/CET of both counters (HIGH = counting enabled, LOW = frozen for reading)
Reading sequence (Arduino pseudocode):
const int COUNT_ENABLE_PIN = 7; // HIGH = count, LOW = freeze
const int RESET_PIN = 8; // LOW = reset (active-LOW CLR̅)
// Count bits connected to digital pins 2-9 (8 bits total)
const int COUNT_PINS[] = {2,3,4,5,6, A0,A1,A2}; // QA0-QD0, QA1-QD1
uint8_t readCount() {
uint8_t result = 0;
for (int i = 0; i < 8; i++) {
if (digitalRead(COUNT_PINS[i])) result |= (1 << i);
}
return result;
}
void loop() {
// Enable counting for 100ms measurement window
digitalWrite(COUNT_ENABLE_PIN, HIGH);
delay(100);
// Freeze counter for reading
digitalWrite(COUNT_ENABLE_PIN, LOW);
// Read the 8-bit count
uint8_t count = readCount();
Serial.print("Count: ");
Serial.println(count);
// Reset for next cycle
digitalWrite(RESET_PIN, LOW); // CLR̅ = LOW → resets to 0
delayMicroseconds(100); // Hold reset long enough (> 1 clock cycle)
digitalWrite(RESET_PIN, HIGH); // Release reset
// Enable counting again
digitalWrite(COUNT_ENABLE_PIN, HIGH);
}Note: CEP and CET are both tied to COUNT_ENABLE_PIN for proper counting control. CLR̅ is synchronous on 74HC163 — a clock edge is needed to actually clear. For asynchronous instant clear, use the 74HC161 which has an asynchronous CLR̅. Alternatively, give a brief CLK pulse while CLR̅ is LOW.
Troubleshooting Counter Circuits
Counter counts by 2 or more per button press: Switch bounce. The button press creates multiple rising edges. Add RC debounce (10kΩ + 100nF) + Schmitt trigger (74HC14), or use NAND SR latch debounce.
Counter randomly skips counts or counts backward: Floating inputs on unused flip-flop control pins (PRE̅ or CLR̅). Both PRE̅ and CLR̅ must be tied HIGH (VCC) through at least 10kΩ resistors when not in use. A floating CLR̅ that drifts LOW resets the counter unexpectedly.
Counter resets to zero spontaneously during counting: Supply voltage glitch. Add 100nF ceramic decoupling capacitor directly at each IC’s VCC pin. A voltage dip that crosses below the UVLO threshold resets flip-flops.
Counter output bits appear reversed (counting down instead of up): Clock edge polarity. If using positive-edge-triggered flip-flops, clock each stage from Q̄ of the previous stage (not Q). If all LEDs are in correct order but the count appears inverted (11, 10, 9… instead of 1, 2, 3…), check which Q output is the LSB — Q0 should be the fastest-changing bit.
74HC163 won’t count: Check CEP and CET — both must be HIGH to enable counting. Check PE̅ — must be HIGH to prevent parallel load (if PE̅ is floating LOW, the counter constantly loads the A-D input values instead of counting). Check CLR̅ — if held LOW, counter stays reset.
LED display shows wrong digits (skips 0 or shows wrong segments): 74HC4511 BCD decoder inputs are connected in wrong order. Verify A connects to QA (LSB), B to QB, C to QC, D to QD (MSB). Swapping any two inputs produces garbled display output.
Summary
Counter circuits built from flip-flops count by connecting toggle flip-flops (D flip-flop with Q̄ fed back to D) in a chain, where each stage divides its clock by 2. The full chain produces binary counts: 2 flip-flops count 0–3, 4 flip-flops count 0–15, 8 flip-flops count 0–255.
Ripple (asynchronous) counters chain each flip-flop’s Q̄ output to the next stage’s clock. They are simple — one 74HC74 IC provides a 2-bit counter, two ICs provide a 4-bit counter — but suffer from propagation delay (N × t_pCLK-Q for N stages) and transient glitching during multi-bit transitions. They work well for low-speed applications and frequency division.
Synchronous counters clock all flip-flops from a common clock, computing each stage’s enable from the AND of all lower bits. No ripple, no glitches, full-speed operation. The 74HC163 implements a complete synchronous 4-bit counter with parallel load, synchronous reset, and terminal count output for cascading — two ICs provide an 8-bit counter, four provide a 16-bit counter.
Modulo-N counters reset at a specified count using a simple NAND gate decoder connected to CLR̅. Decade counters (modulo-10) use NAND(QD, QB); modulo-6 counters use NAND(QC, QB). Cascading these stages builds 60-second timers, clock circuits, and any other non-power-of-2 counting application.
