A full adder is a combinational logic circuit that adds three single-bit inputs — two data bits (A and B) and a carry-in (C_in) from a less significant bit position — producing a sum bit (SUM) and a carry-out (C_out). Unlike the half adder which only handles two inputs, the full adder’s three-input capability makes it the correct building block for every bit position beyond the least significant in multi-bit binary addition, enabling arbitrarily wide arithmetic by chaining full adders in series or trees.
Introduction: The Circuit That Makes Multi-Bit Addition Work
In the previous article, the half adder emerged from the observation that binary addition of two bits follows the XOR rule for the sum and the AND rule for the carry. The half adder implements this perfectly — two gates, two outputs, correct for all four input combinations. For a single-bit addition in isolation, nothing more is needed.
The moment you want to add numbers wider than one bit, the half adder’s limitation becomes apparent. Consider adding two 8-bit numbers: you process column by column, starting from the least significant bit (bit 0) and working left. The half adder handles bit 0 fine — it has no carry coming from the right. But bit 1 might receive a carry from bit 0. Bit 2 might receive a carry from bit 1. Every column except the first potentially receives a carry digit from the column to its right.
A circuit that handles only two inputs — A and B — is fundamentally insufficient for these middle and upper columns. What is needed is a circuit that can add three inputs simultaneously: A, B, and whatever carry arrives from the right. This is the full adder.
The word “full” is deliberate: the full adder is the complete, general-purpose building block for binary addition. The half adder is a special case — a full adder with carry-in permanently wired to zero. Understanding the full adder in depth means understanding the mechanism by which all digital arithmetic operates, from the 4-bit counter in a timer circuit to the 64-bit floating-point unit in a modern processor.
This article develops the full adder from its truth table through its Boolean derivation, gate implementation, carry behavior under all conditions, cascading into multi-bit adders, carry lookahead for speed, overflow detection for both unsigned and signed arithmetic, and extension into subtraction and comparison. Five complete design examples build progressively from a single full adder verification to a working 4-bit ALU slice.
The Full Adder Truth Table: All Eight Cases
Defining the Inputs and Outputs
A full adder has three single-bit inputs:
- A: One operand bit
- B: Second operand bit
- C_in: Carry-in from the adjacent less-significant bit position
And two single-bit outputs:
- SUM: The sum of A + B + C_in, modulo 2 (the current-position digit)
- C_out: The carry-out to the adjacent more-significant bit position (overflow from this column)
Three inputs → 2³ = 8 rows in the truth table.
The Complete Truth Table
| A | B | C_in | A+B+C_in (decimal) | SUM | C_out |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 2 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 2 | 0 | 1 |
| 1 | 1 | 0 | 2 | 0 | 1 |
| 1 | 1 | 1 | 3 | 1 | 1 |
Reading the Pattern
SUM column: Output is HIGH when the decimal sum is ODD (1 or 3). Output is LOW when the decimal sum is EVEN (0 or 2). This is the three-input XOR pattern — HIGH when an odd number of inputs are HIGH.
C_out column: Output is HIGH when the decimal sum is ≥ 2 — when two or more inputs are simultaneously HIGH. This is the majority function: C_out = 1 whenever a majority of inputs are 1.
Deriving the Boolean Expressions
SUM:
Directly from the XOR observation:
SUM = A ⊕ B ⊕ C_inVerification: When exactly 1 or exactly 3 inputs are HIGH, XOR gives 1. When 0 or 2 inputs are HIGH, XOR gives 0. This matches the truth table exactly. ✓
C_out:
The majority function — output HIGH when two or more of three inputs are HIGH. Writing the SoP (Sum of Products) from the four rows where C_out = 1:
C_out = Ā·B·C_in + A·B̄·C_in + A·B·C̄_in + A·B·C_inSimplification using K-map:
Three-variable K-map for C_out:
BC_in=00 BC_in=01 BC_in=11 BC_in=10
A=0 | 0(m0) | 0(m1) | 1(m3) | 0(m2) |
A=1 | 0(m4) | 1(m5) | 1(m7) | 1(m6) |Grouping:
Group 1 — cells m3 and m7 (vertical pair in BC_in=11 column):
- A varies → eliminated; B=1; C_in=1
- Term: B·C_in
Group 2 — cells m5 and m7 (vertical pair sharing A=1 row, BC_in=01 and BC_in=11): Wait — m5 is (A=1, BC_in=01) and m7 is (A=1, BC_in=11). These are adjacent.
- A=1; B varies; C_in=1
- Term: A·C_in
Group 3 — cells m6 and m7 (horizontal pair in A=1 row, BC_in=11 and BC_in=10):
- A=1; B=1; C_in varies → eliminated
- Term: A·B
All four 1-cells (m3, m5, m6, m7) covered. Each is covered by at least one group.
Simplified C_out:
C_out = A·B + A·C_in + B·C_inThis is the majority function: C_out is HIGH when any two (or all three) of A, B, C_in are HIGH — exactly what we expect for overflow from a column sum.
An Alternative C_out Expression
Using the generate-propagate framework (introduced in carry lookahead later):
C_out = A·B + (A ⊕ B)·C_inWhere:
- A·B = Generate (G): this bit position generates a carry regardless of carry-in — when both A and B are 1, their sum always produces a carry
- A ⊕ B = Propagate (P): this bit position propagates an incoming carry — when exactly one of A, B is 1, an incoming C_in is passed through
Proof of equivalence:
A·B + (A⊕B)·C_in
= A·B + (Ā·B + A·B̄)·C_in
= A·B + Ā·B·C_in + A·B̄·C_inExpand A·B + A·C_in + B·C_in:
A·B + A·C_in·(B+B̄) + B·C_in·(A+Ā)
= A·B + A·B·C_in + A·B̄·C_in + A·B·C_in + Ā·B·C_in
= A·B + A·B̄·C_in + Ā·B·C_in (using A·B·C_in absorbed by A·B)Both simplify to the same expression. ✓ The generate-propagate form is more useful for carry lookahead design.
The Full Adder Gate Circuit
Implementation from Basic Gates
Using XOR, AND, and OR:
Gate 1 (XOR): A, B → TEMP = A ⊕ B
Gate 2 (XOR): TEMP, C_in → SUM = A ⊕ B ⊕ C_in
Gate 3 (AND): A, B → G = A·B (generate)
Gate 4 (AND): TEMP, C_in → P_carry = (A⊕B)·C_in (propagated carry)
Gate 5 (OR): G, P_carry → C_out = A·B + (A⊕B)·C_inFive gates total. The TEMP signal (A⊕B) is shared between Gate 2 and Gate 4 — computed once, used twice. This sharing is key to the efficient two-half-adder structure.
The Two-Half-Adder Structure
Recognize that Gates 1–2 form Half Adder 1 (HA1) and Gates 3–4–5 with HA2 form the second half:
Half Adder 1:
- Inputs: A, B
- SUM1 = A ⊕ B (XOR gate)
- CARRY1 = A · B (AND gate)
Half Adder 2:
- Inputs: SUM1, C_in
- SUM = SUM1 ⊕ C_in = A ⊕ B ⊕ C_in (XOR gate)
- CARRY2 = SUM1 · C_in = (A⊕B)·C_in (AND gate)
OR gate:
- C_out = CARRY1 + CARRY2 = A·B + (A⊕B)·C_in
Total: 2 XOR + 2 AND + 1 OR = 5 gates. Same count as direct implementation, same functionality, but the two-half-adder decomposition makes the circuit’s structure intuitive and modular.
Why the OR Gate Cannot Produce a False Carry
CARRY1 and CARRY2 can never simultaneously be HIGH, so the OR could theoretically be replaced by XOR with identical results:
Proof: CARRY1 = A·B (both HIGH). CARRY2 = (A⊕B)·C_in. For both to be HIGH simultaneously: A·B = 1 requires A=1 and B=1. But A⊕B = 1⊕1 = 0. So (A⊕B)·C_in = 0·C_in = 0. CARRY2 can never be HIGH when CARRY1 is HIGH. ✓
Therefore CARRY1·CARRY2 = 0 always, meaning OR and XOR produce identical results for this specific input combination. In practice, OR is used because it is the correct logical description.
Gate Counts and Critical Path
The critical path (longest delay path from input to output) determines the adder’s maximum speed:
SUM critical path: A → Gate1(XOR) → Gate2(XOR) → SUM = 2 gate delays
C_out critical path:
- Via generate: A → Gate3(AND) → Gate5(OR) → C_out = 2 gate delays
- Via propagate + carry-in: A → Gate1(XOR) → Gate4(AND) → Gate5(OR) → C_out = 3 gate delays
The C_out worst-case path is 3 gate delays (through the propagate path: XOR → AND → OR).
For 74HC logic (each gate ~7–8ns):
- SUM delay: 2 × 8ns = 16ns
- C_out delay: 3 × 8ns = 24ns
The carry propagation delay (24ns) is what limits ripple-carry adder speed.
Understanding Carry Behavior: Generate, Propagate, and Kill
The Three Carry Cases
Every bit position of a full adder falls into one of three carry behaviors:
Generate (G): A·B = 1 (both inputs HIGH)
- This position produces a carry-out regardless of carry-in
- C_out = 1 whether C_in = 0 or 1
- The carry is “generated” here
Propagate (P): A⊕B = 1 (exactly one input HIGH)
- This position passes carry-in through to carry-out
- C_out = C_in (if C_in=1, carry-out=1; if C_in=0, carry-out=0)
- The carry is “propagated” through this position
Kill (K): A=0 AND B=0 (both inputs LOW, which also includes when A⊕B=0 and A·B=0)
- Actually Kill occurs only when both A=0 and B=0 AND the position doesn’t generate
- C_out = 0 regardless of C_in
- The carry is “killed” (absorbed) here
Wait — more precisely:
- Generate: G = A·B — C_out=1 regardless of C_in
- Propagate: P = A⊕B (when G=0) — C_out follows C_in
- Kill: G=0 AND P=0, meaning A=B=0 — C_out=0 regardless
Truth table of carry behavior:
| A | B | Behavior | C_out when C_in=0 | C_out when C_in=1 |
|---|---|---|---|---|
| 0 | 0 | Kill | 0 | 0 |
| 0 | 1 | Propagate | 0 | 1 |
| 1 | 0 | Propagate | 0 | 1 |
| 1 | 1 | Generate | 1 | 1 |
Importance for Timing Analysis
In a ripple adder, carry propagation through a long chain of “Propagate” positions takes maximum time. The worst case is when every bit position propagates the carry from bit 0 to bit N. For example, adding 0111…1 + 0000…1 (all ones plus one) causes a carry to ripple through every bit position:
0111 1111 (127)
+ 0000 0001 (1)
-----------
1000 0000 (128)Every bit position propagates. The carry ripples from bit 0 to bit 7, taking 8 × 24ns = 192ns for an 8-bit adder. This worst case determines the maximum clock frequency for any ripple-carry design.
Carry Lookahead: Computing All Carries in Parallel
The Core Insight
Instead of waiting for carry to ripple through each stage, carry lookahead computes all carry bits simultaneously using the generate (G) and propagate (P) signals from all bit positions at once. Since G and P depend only on A and B inputs (not on carry-in), they are available immediately — and carry for each position can be computed in two gate levels from these signals.
Carry Equations for a 4-bit Group
Define for each bit position i:
G_i = A_i · B_i (generate)
P_i = A_i ⊕ B_i (propagate)The carry into each position (using C_0 as the initial carry-in):
C_1 = G_0 + P_0·C_0
C_2 = G_1 + P_1·C_1
= G_1 + P_1·(G_0 + P_0·C_0)
= G_1 + P_1·G_0 + P_1·P_0·C_0
C_3 = G_2 + P_2·C_2
= G_2 + P_2·G_1 + P_2·P_1·G_0 + P_2·P_1·P_0·C_0
C_4 = G_3 + P_3·C_3
= G_3 + P_3·G_2 + P_3·P_2·G_1 + P_3·P_2·P_1·G_0 + P_3·P_2·P_1·P_0·C_0Each carry equation is a multi-level AND-OR expression computable in exactly two gate levels (one AND level, one OR level) — regardless of bit position. C_4 requires the same two gate levels as C_1, where the ripple adder would need four carry stages.
Gate Structure of a 4-bit CLA Unit
Generate and propagate computation (1 gate level):
- 4× AND gates: G0=A0·B0, G1=A1·B1, G2=A2·B2, G3=A3·B3
- 4× XOR gates: P0=A0⊕B0, P1=A1⊕B1, P2=A2⊕B2, P3=A3⊕B3
Carry computation (2 gate levels — AND then OR): C_1: 1 AND (P0·C0) + 1 OR with G0 = 2 levels C_2: 2 ANDs (P1·G0, P1·P0·C0) + 1 OR with G1 = 2 levels C_3: 3 ANDs + 1 OR = 2 levels C_4: 4 ANDs + 1 OR = 2 levels (but the AND for P3·P2·P1·P0·C0 is 5-input)
Sum computation (using pre-computed P and C): SUM_i = P_i ⊕ C_i (1 XOR gate per bit — one more gate level)
Total delay for 4-bit CLA: 1 (G/P compute) + 2 (carry compute) + 1 (sum from P and C) = 4 gate levels
Compare to ripple adder: bit 3 sum = 3 carry stages × 3 levels each + 2 sum levels = 11 levels for the MSB sum. CLA gives 4 levels — nearly 3× faster.
The 74HC182: Carry Lookahead Unit
The 74HC182 is a dedicated carry lookahead generator IC that accepts G and P signals from four bit positions and outputs the four carry signals (C1, C2, C3, C4) simultaneously:
- Inputs: G0–G3, P0–P3, C_n (group carry-in)
- Outputs: C_n+1, C_n+2, C_n+3, C_n+4 (four carry signals), G_group, P_group
- The group G and P outputs allow cascading 74HC182s for wider words (16-bit, 32-bit)
- Propagation delay: ~15ns at 5V — same delay for all four carry outputs regardless of bit position
Using 74HC182 with four full adders: Replace the ripple carry chain with:
- Compute G_i and P_i from each full adder (or separately from A_i, B_i)
- Feed G and P signals to 74HC182
- 74HC182 produces C1–C4 simultaneously
- Feed each C_i directly to its corresponding full adder’s carry-in
This eliminates carry ripple entirely for the 4-bit group.
Group Carry Lookahead for Wider Words
For 16-bit addition using four 4-bit CLA groups:
- Each 4-bit group produces group-level G and P signals
- A second-level 74HC182 computes carries between groups
- Total delay: local G/P + group carry + sum ≈ 6–8 gate levels regardless of word width
Modern processors use 3–4 levels of carry lookahead hierarchy for 64-bit addition, achieving complete 64-bit addition in approximately 6–8 gate levels — roughly 50–100ps in advanced CMOS processes.
Multi-Bit Adder Design: Ripple vs. Lookahead
When to Use Each Architecture
Ripple-carry adder (simple, slow):
- Best for: Low-power, non-timing-critical designs, small bit widths (4-bit or less)
- Advantages: Minimal gate count, simple layout, predictable structure
- Disadvantages: O(N) delay — doubles with each doubling of word width
- IC: 74HC283 (4-bit, ~15ns carry propagation)
- Use when: Speed is not critical, or bit width is ≤ 8 bits at low clock rates
Carry lookahead adder (fast, moderate complexity):
- Best for: 8–16 bit addition where speed matters
- Advantages: O(log N) delay — logarithmic scaling
- Disadvantages: More gates, more complex routing
- IC: 74HC283 + 74HC182 for carry lookahead
- Use when: Clock frequency > 20MHz with 8+ bit words
Prefix adder (fastest, complex):
- Best for: On-chip ALUs in processors (64-bit, 100MHz–5GHz)
- Implementations: Kogge-Stone, Brent-Kung, Sklansky
- Advantages: O(log N) delay with optimal constants
- Disadvantages: High gate count and wire complexity
- Use when: Maximum speed required, implementation is ASIC or FPGA
8-Bit Ripple-Carry Adder Using Two 74HC283s
Circuit: Two 74HC283 ICs cascaded:
- IC1: adds A3-A0 + B3-B0, C0=0, produces S3-S0, C4
- IC2: adds A7-A4 + B7-B4, C0=IC1_C4, produces S7-S4, C8 (overflow)
Total propagation delay:
- IC1 carry-out: ~15ns
- IC2 sum outputs: IC1 delay (15ns) + IC2 sum delay (~20ns) = 35ns total for MSB sum
Maximum reliable clock frequency with 50% margin: f = 1/(35ns × 2) ≈ 14MHz.
Adequate for most 8-bit applications at clock rates below 10MHz (microcontrollers, counters, displays).
16-Bit Lookahead Adder
Four 74HC283s (for the four 4-bit groups) + one 74HC182 (for group carry lookahead):
Structure:
- 74HC283 #1: bits 3-0, C0=0 → S3-S0, G0_group, P0_group (derived from carries)
- 74HC283 #2: bits 7-4, C4=from 74HC182 → S7-S4
- 74HC283 #3: bits 11-8, C8=from 74HC182 → S11-S8
- 74HC283 #4: bits 15-12, C12=from 74HC182 → S15-S12
The 74HC182 receives group G and P from each 74HC283 (some 74HC283 variants provide these directly; otherwise, external logic computes them).
Total delay: ~30ns for full 16-bit sum — versus ~60ns for four cascaded 74HC283s in ripple configuration. A 2× speed improvement.
Overflow and Status Flags
The Four Standard ALU Flags
Every processor ALU produces four status flags from its adder, stored in a status/flags register:
Carry Flag (C): The carry-out from the most significant bit position. Indicates unsigned overflow — result exceeds the maximum value for the word width.
C = C_out_MSBFor unsigned 8-bit addition: 200 + 100 = 300. 300 > 255, so C=1 (result wraps to 44).
Zero Flag (Z): The result is all zeros.
Z = ̄S7 · ̄S6 · ̄S5 · ̄S4 · ̄S3 · ̄S2 · ̄S1 · ̄S0OR: Z = NOR(S7, S6, S5, S4, S3, S2, S1, S0)
Implemented as a single 8-input NOR gate (or two 4-input NORs followed by one 2-input NOR).
Sign Flag (N or S): The MSB of the result (the sign bit in two’s complement representation).
N = S_MSBSimply the MSB output of the adder — no additional logic needed.
Overflow Flag (V or OV): Signed arithmetic overflow — the mathematical result exceeds the representable range of signed numbers. For N-bit two’s complement: range is -2^(N-1) to +2^(N-1)-1.
Signed overflow occurs when:
- Two positive numbers add to give a negative result (carry into MSB but not out)
- Two negative numbers add to give a positive result (carry out of MSB but not into MSB)
Detection:
V = C_out_MSB ⊕ C_out_{MSB-1}The XOR of the carry INTO the MSB position and the carry OUT OF the MSB position:
- If C_in_MSB = 0 and C_out_MSB = 1: result wrapped from positive to negative → overflow
- If C_in_MSB = 1 and C_out_MSB = 0: result wrapped from negative to positive → overflow
- If they match: no signed overflow
Example (8-bit signed): 100 + 100 = 200. But 200 > 127 (max signed 8-bit). Result = -56 in two’s complement. C_out_MSB = 0 (no carry out), C_in_MSB = 1 (carry into bit 7). V = 0 ⊕ 1 = 1 → overflow detected ✓.
Example: 50 + 50 = 100. Both positive, result positive, within range. C_out_MSB = 0, C_in_MSB = 0. V = 0 ⊕ 0 = 0 → no overflow ✓.
Implementing Flags in Hardware
For a 4-bit adder (using 74HC283):
Carry flag: C = pin 9 of 74HC283 (C4 output) — direct connection.
Zero flag:
Z = NOR(S3, S2, S1, S0)One 74HC4002 (4-input NOR) gives Z directly.
Sign flag: N = S3 (MSB sum output) — direct wire.
Overflow flag:
V = C4 ⊕ C3Where C3 is the carry INTO the MSB (bit 3). C3 is available as the carry-out of the 3-bit group — some adder configurations provide this intermediate carry, others require tapping the full adder’s carry signal directly.
One 74HC86 gate computes V from C4 and C3.
Full Adder Applications Beyond Addition
Two’s Complement Subtraction Review
From Article 83: A – B = A + B̄ + 1. In a full adder-based ALU:
- B inputs pass through XOR gates with a SUB control: B_eff = B ⊕ SUB
- Carry-in C0 = SUB (adds the +1 when subtracting)
- When SUB=0: adds A + B + 0 = A + B
- When SUB=1: adds A + B̄ + 1 = A – B in two’s complement
Increment and Decrement
Increment (A + 1): Set B=0 (all zeros) and C_in=1. Result = A + 0 + 1 = A + 1.
Decrement (A – 1): Set B=1 (all ones = 0xFF for 8-bit) and C_in=0, then ADD. A + 1111…1 + 0 = A + (−1 in two’s complement) = A − 1.
Or equivalently: set B=0, C_in=0, and use the subtraction mode: A – 0 – carry… Actually, simpler: use B=1111…1 directly. In most ALUs, increment/decrement are special cases handled by multiplexing the B input.
Comparator Operations
Two numbers A and B are compared by computing A – B and examining the flags:
- A = B: Z flag = 1 (result is zero)
- A > B (unsigned): C flag = 0 (no borrow from the subtraction)
- A < B (unsigned): C flag = 1 (borrow occurred)
- A > B (signed): N flag = V flag (sign equals overflow — positive result without overflow)
- A < B (signed): N flag ≠ V flag (negative result or overflow)
- A ≥ B (signed): N ⊕ V = 0
- A < B (signed): N ⊕ V = 1
This is why processors don’t need separate comparator circuits — the adder with subtraction mode plus flag logic handles all comparison operations. The conditional branch instructions (jump if equal, jump if greater, jump if carry, etc.) simply check the appropriate flag combinations.
Arithmetic Shift and Rotate
While not directly part of the adder, shifting left by one bit is equivalent to multiplying by 2 (in binary), and the carry-out provides the overflow bit. Similarly, rotating through carry uses the carry flag as an extra bit. The adder’s carry-in and carry-out bits connect to the shift register’s LSB and MSB inputs in many processor architectures.
Complete Design Examples
Design Example 1: Single Full Adder — Complete Verification
Objective: Build a single full adder from discrete gates on a breadboard and verify all 8 truth table combinations.
Components:
- 1× 74HC86 (Quad XOR) — uses 2 gates
- 1× 74HC08 (Quad AND) — uses 2 gates
- 1× 74HC32 (Quad OR) — uses 1 gate
- 3× SPDT switches (A, B, C_in)
- 2× LEDs + 470Ω resistors (SUM, C_out)
- 2× 100nF decoupling capacitors
- 5V supply
Gate connections:
Gate XOR1 (74HC86 gate 1): pins 1,2 → A,B; pin 3 → TEMP (A⊕B)
Gate XOR2 (74HC86 gate 2): pins 4,5 → TEMP,C_in; pin 6 → SUM
Gate AND1 (74HC08 gate 1): pins 1,2 → A,B; pin 3 → G (generate)
Gate AND2 (74HC08 gate 2): pins 4,5 → TEMP,C_in; pin 6 → P_carry (propagated carry)
Gate OR1 (74HC32 gate 1): pins 1,2 → G,P_carry; pin 3 → C_outNote the shared TEMP signal: pin 3 of 74HC86 gate 1 connects to both pin 4 of 74HC86 gate 2 AND pin 5 of 74HC08 gate 2. This single connection fan-out is within 74HC specifications (fan-out 25+).
Test procedure and expected results:
| Test | A | B | C_in | Expected SUM | Expected C_out | LED pattern |
|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0 | 0 | 0 | both off |
| 2 | 0 | 0 | 1 | 1 | 0 | SUM on |
| 3 | 0 | 1 | 0 | 1 | 0 | SUM on |
| 4 | 0 | 1 | 1 | 0 | 1 | C_out on |
| 5 | 1 | 0 | 0 | 1 | 0 | SUM on |
| 6 | 1 | 0 | 1 | 0 | 1 | C_out on |
| 7 | 1 | 1 | 0 | 0 | 1 | C_out on |
| 8 | 1 | 1 | 1 | 1 | 1 | both on |
Test 8 is the critical one: A=1, B=1, C_in=1 → decimal 3. SUM LED and C_out LED both on, representing binary “11” = 3. ✓
Design Example 2: 4-Bit Full Adder with Flag Output
Objective: Build a 4-bit adder using a 74HC283 with carry, zero, sign, and overflow flag outputs.
Components:
- 1× 74HC283 (4-bit adder)
- 1× 74HC86 (for V flag: V = C4 ⊕ C3, and for carry-in isolation)
- 1× 74HC4002 (4-input NOR for Z flag)
- 1× 74HC04 (for N flag buffer and spare)
- 8× SPDT DIP switches (A3-A0, B3-B0)
- 9× LEDs + 470Ω resistors (S3-S0, C=C4, Z, N, V)
- 100nF decoupling on each IC
Key connections:
74HC283:
A inputs ← switches A3-A0
B inputs ← switches B3-B0
C0 (pin 7) → GND (addition mode, no carry-in)
S outputs → 4 LEDs + flag inputs
C4 output → Carry LED + V flag computation
Flag logic:
Z = NOR(S3, S2, S1, S0) [74HC4002 pin inputs: S3-S0]
N = S3 [direct LED connection]
V = C4 ⊕ C3 [74HC86 — need C3 signal]Getting C3 (carry into MSB):
The 74HC283 does not expose intermediate carry signals directly. To obtain C3, use the relationship:
C_out_bit2 = C3 = carry INTO bit 3This requires either: (a) Building from discrete full adders where C3 is directly accessible, OR (b) Computing C3 = (A2·B2) + ((A2⊕B2)·(A1·B1 + (A1⊕B1)·(A0·B0 + (A0⊕B0)·C0))) which requires several gates — complex for a demo circuit, OR (c) Approximating V using only C4 and the MSB inputs: V = C4 ⊕ (A3 ⊕ B3 ⊕ S3). This works because if all three (A3, B3, S3) differ from C4 in a specific way, overflow has occurred. Specifically: V = (A3 · B3 · S3̄) + (Ā3 · B̄3 · S3) — positive overflow + negative overflow. This requires 2 AND gates and 1 OR gate.
Simpler overflow formula:
V = (A3 · B3 · ̄S3) + (Ā3 · ̄B3 · S3)- A3=1, B3=1, S3=0: added two positives, got negative → overflow
- A3=0, B3=0, S3=1: added two negatives, got positive → overflow
This uses only A3, B3, S3 — all directly available — with 2 three-input AND gates and one OR gate.
Testing the overflow flag:
Set A = 0111 (7, max positive 4-bit signed) and B = 0001 (1):
- Sum = 0111 + 0001 = 1000 = -8 in two’s complement
- V should = 1 (positive + positive = negative → overflow)
- A3=0, B3=0, S3=1 → Ā3·B̄3·S3 = 1 ✓
Set A = 0011 (3) and B = 0100 (4):
- Sum = 0111 (7) — valid positive result
- A3=0, B3=0, S3=0 → neither overflow term active → V=0 ✓
Design Example 3: 4-Bit Magnitude Comparator Using Full Adder
Objective: Compare two 4-bit unsigned numbers A and B to determine A>B, A=B, A<B using a 74HC283 in subtraction mode.
Principle: Compute A – B using the adder/subtractor configuration. Examine carry-out and zero flag:
- C4=1, Z=0: No borrow → A ≥ B. If also Z=0 → A > B
- C4=1, Z=1: A = B (result is zero, no borrow — actually this means A=B exactly)
- C4=0: Borrow occurred → A < B
Wait — let me clarify the carry/borrow relationship for subtraction:
In the adder/subtractor A + B̄ + 1:
- If A ≥ B: mathematical result ≥ 0. The two’s complement addition produces a carry-out of 1. C4=1 means no borrow → A ≥ B
- If A < B: mathematical result < 0. No carry-out. C4=0 means borrow → A < B
So for unsigned comparison:
A_GREATER_OR_EQUAL = C4 (carry out from subtraction)
A_LESS = ̄C4 (no carry = borrow = A < B)
A_EQUAL = Z (zero flag — result is zero means A = B)
A_GREATER = C4 · ̄Z (≥ but not equal)Gate implementation for the three comparison outputs:
C4 → A_GE output (A greater than or equal)
̄C4 → 74HC04 → A_LT output (A less than)
NOR(S3,S2,S1,S0) → Z → A_EQ output (A equal to B)
AND(C4, ̄Z) → A_GT output (A greater than)ICs: 74HC283 + 74HC86 (XOR for B inversion: B_eff = B ⊕ 1111) + 74HC04 (NOT for ̄C4) + 74HC4002 (NOR for Z) + 74HC08 (AND for A_GT).
Testing:
A = 1010 (10), B = 0110 (6):
- B_eff = B ⊕ 1111 = 1001, C0=1
- 1010 + 1001 + 1 = 10100 → S=0100, C4=1
- Z = NOR(0,1,0,0) = 0
- A_GE=1, A_LT=0, A_EQ=0, A_GT = 1·1 = 1 ✓ (10 > 6)
A = 0101 (5), B = 0101 (5):
- B_eff = 1010, C0=1
- 0101 + 1010 + 1 = 10000 → S=0000, C4=1
- Z = NOR(0,0,0,0) = 1
- A_GE=1, A_LT=0, A_EQ=1, A_GT = 1·0 = 0 ✓ (5 = 5)
A = 0011 (3), B = 0111 (7):
- B_eff = 1000, C0=1
- 0011 + 1000 + 1 = 01100 → S=1100, C4=0
- A_GE=0, A_LT=1, A_EQ=0, A_GT=0 ✓ (3 < 7)
Design Example 4: 8-Bit Adder/Subtractor with Full Flag Set
Objective: Build a complete 8-bit arithmetic unit using two 74HC283s with add/subtract control, carry, zero, sign, and overflow flags.
Components:
- 2× 74HC283 (4-bit adder — cascade for 8-bit)
- 2× 74HC86 (8 XOR gates for B inversion, uses all 8)
- 1× 74HC02 (NOR gates — combine zero flag from two 4-bit groups)
- 1× 74HC04 (inverter for SUB → ̄SUB, and N flag buffer)
- 1 SUB control line
Architecture:
A7-A4, B7-B4 ──────────┐ A3-A0, B3-B0 ─────────────┐
↓ ↓
B7-B4 ⊕ SUB → B7-B4_eff B3-B0 ⊕ SUB → B3-B0_eff
↓ ↓
74HC283 HIGH 74HC283 LOW
C4=from LOW C0=SUB
S7-S4 → S3-S0 →
C8 (overflow) → C4 → HIGH adder C0Flag generation:
Carry (C) = C8 (from high 74HC283)
Zero (Z) = NOR(S7,S6,S5,S4,S3,S2,S1,S0)
= NOR( NOR(S7,S6,S5,S4), NOR(S3,S2,S1,S0) )
= Two 74HC4002 + one 74HC02 gate
Sign (N) = S7 (MSB output)
Overflow (V) = C8 ⊕ C7
where C7 = carry out of bit 6 = carry INTO bit 7Getting C7: It’s the carry-out of the lower 3 bits of the high 74HC283. The 74HC283 doesn’t expose C7 directly, but it can be derived:
C7 = G6 + P6·G5 + P6·P5·G4 + P6·P5·P4·C4This requires additional gates. A practical simplification: compute V using the MSB inputs and output:
V = (A7·B7·̄S7) + (Ā7·B̄7·S7) [for addition mode]
V = (A7·̄B7·̄S7) + (Ā7·B7·S7) [for subtraction mode, B7 already inverted]Since B7_eff = B7 ⊕ SUB, the unified formula for both modes uses B7_eff:
V = (A7·B7_eff·̄S7) + (Ā7·B̄7_eff·S7)Three gates: 2× AND (3-input) + 1× OR.
Example: -64 – 65 in 8-bit signed arithmetic:
-64 = 11000000, -65 = 10111111
In subtraction mode: A + (-65)̄ + 1 = A + B̄ + 1
B = 10111111, B̄ = 01000000
A + B̄ + 1 = 11000000 + 01000000 + 1 = 1_00000001
S = 00000001, C8=1
V check: A7=1, B7_eff=0 (B7=1, inverted because SUB=1 → B7_eff=0), S7=0
V = (1·0·1) + (0·1·0) = 0 + 0 = 0Hmm, -64 – 65 = -129, which DOES overflow 8-bit signed (-128 to +127). Let me recheck.
-64 = 0xC0 = 11000000 ✓ -65 = 0xBF = 10111111 ✓
A – B in two’s complement: A + B̄ + 1 B̄ = 01000000 11000000 + 01000000 + 1 = 100000001 → S = 00000001 (+1), C8=1
Result +1, but -64 – 65 = -129. The result wrapped to +1 — OVERFLOW!
V check with formula: A7=1, B7_eff = B7⊕SUB = 1⊕1 = 0, S7 = 0 V = (A7·B7_eff·̄S7) + (Ā7·B̄7_eff·S7) = (1·0·1) + (0·1·0) = 0
The formula gives V=0 but we know there’s overflow. The formula V = (A7·B7_eff·̄S7) + (Ā7·B̄7_eff·S7) checks for two positives giving negative or two negatives giving positive. Here A7=1 (negative) and B7_eff=0 (positive) — mixed signs, normally no overflow possible… but this IS a subtraction case.
The issue is that after B inversion for subtraction, B7_eff=0 representing a positive value (since -(-65) = +65 = 01000001). Adding -64 + (+65) where + means in the inverted form… actually -64 + B̄ + 1 = -64 – (-65) wait that’s wrong.
Let me re-examine: A – B = A + B̄ + 1.
If A = -64 and B = -65: A – B = -64 – (-65) = -64 + 65 = +1. That’s NOT overflow. My initial problem statement was wrong: -64 – (-65) = +1, which is within range.
If the intent was -64 + (-65) = -129 (overflow), then it’s an ADDITION problem: A = -64 = 11000000, B = -65 = 10111111 A + B = 11000000 + 10111111 = 101111111 → S=01111111=+127, C8=1
V check: A7=1, B7_eff=1 (no subtraction, B passes unchanged), S7=0 V = (A7·B7_eff·̄S7) + … = (1·1·1) + … = 1 ✓ Overflow correctly detected!
The design is correct. The example works for addition of two negatives giving wrong positive result. ✓
Design Example 5: Cascading Full Adders for BCD Addition Correction
Objective: Implement BCD (Binary-Coded Decimal) addition for two decimal digits using two 74HC283 stages — one for the raw binary sum, one for the BCD correction — with correct decimal carry-out.
From the analysis in Article 83:
Stage 1 — Raw binary sum: 74HC283 #1 adds the two 4-bit BCD digits: S = A + B (binary sum, 0–18 range).
Correction detection (when sum > 9):
CORRECT = C4 + (S3·S2) + (S3·S1)Where:
- C4: sum ≥ 16 (always correct)
- S3·S2: sum has bit 3 and bit 2 set → sum ≥ 12
- S3·S1: sum has bit 3 and bit 1 set → sum ≥ 10
Deriving correction detection truth: Values 10–15 (needing correction, all within 4 bits, C4=0):
- 10 = 1010: S3=1, S2=0, S1=1 → S3·S1=1 ✓
- 11 = 1011: S3=1, S2=0, S1=1 → S3·S1=1 ✓
- 12 = 1100: S3=1, S2=1, S1=0 → S3·S2=1 ✓
- 13 = 1101: S3=1, S2=1, S1=0 → S3·S2=1 ✓
- 14 = 1110: S3=1, S2=1, S1=1 → S3·S2=1 ✓
- 15 = 1111: S3=1, S2=1, S1=1 → S3·S2=1 ✓ All correction cases detected. ✓
Stage 2 — BCD correction: 74HC283 #2 adds correction value 0110 (6) when CORRECT=1, else adds 0000:
- B3_corr = 0 (always)
- B2_corr = CORRECT
- B1_corr = CORRECT
- B0_corr = 0 (always)
- C0 = 0
Gate implementation:
- AND gate: S3 · S2 → term1
- AND gate: S3 · S1 → term2
- OR gates: C4 + term1 + term2 → CORRECT
ICs: One 74HC08 (AND gates) + one 74HC32 (OR gates) for correction detection. 74HC283 #1 for raw sum. 74HC283 #2 for BCD correction (B inputs: 0, CORRECT, CORRECT, 0).
Final carry-out (BCD carry):
BCD_CARRY = CORRECT + C4_stage2(Either the first stage needed correction, OR the correction addition itself overflowed.)
In practice: CORRECT already accounts for C4 from stage 1, and C4 from stage 2 handles the case where the correction addition itself overflows (e.g., 9+9=18 → raw=0010+C4=1, correction adds 6 → 0010+0110=1000 with possible carry). BCD_CARRY = CORRECT (since CORRECT already includes C4_stage1 and stage2 carry is handled in the sum bits).
Test: 8 + 7 = 15 → BCD result: carry=1, digit=5
Stage 1: 1000 + 0111 = 1111 = 15, C4=0 CORRECT: S3=1, S2=1, S1=1 → S3·S2=1 → CORRECT=1 Stage 2: 1111 + 0110 = 10101 → S=0101, C4_2=1 BCD result: carry=1, digit=0101=5 ✓ (8+7=15: tens digit 1, units digit 5)
Test: 9 + 9 = 18 → BCD result: carry=1, digit=8
Stage 1: 1001 + 1001 = 10010 → S=0010, C4=1 CORRECT: C4=1 → CORRECT=1 Stage 2: 0010 + 0110 = 1000, C4_2=0 BCD result: carry=1, digit=1000=8 ✓ (9+9=18: tens digit 1, units digit 8)
Common Mistakes in Full Adder Design
Mistake 1: Using a half adder for interior bit positions The half adder has no carry-in input. Every bit position except the LSB can receive a carry. Using a half adder for bit 1, 2, 3… gives wrong results for all input combinations that generate a carry into that position. Build multi-bit adders from full adders (or from the 74HC283 which implements full adders internally with proper carry connections).
Mistake 2: Unconnected carry-in on the LSB The LSB full adder’s carry-in should be tied to GND for addition (C_in=0), or to the SUB signal for subtraction mode. Leaving it floating gives unpredictable results — the floating input may settle to any voltage, causing random carry injection.
Mistake 3: Computing V (overflow) flag incorrectly Overflow is NOT the same as carry. Signed overflow occurs when the carry into the MSB differs from the carry out. Using only C4 for overflow detection is wrong for signed arithmetic. The correct formula V = C_out_MSB ⊕ C_in_MSB requires both the final carry and the carry into the MSB bit.
Mistake 4: Wrong interpretation of subtract result carry flag After subtraction A – B (implemented as A + B̄ + 1):
- C4=1 means NO borrow (A ≥ B)
- C4=0 means BORROW (A < B) This is INVERTED from the intuitive expectation. Processors typically invert the carry flag after subtraction to produce a “borrow” flag with natural polarity. Always clarify whether the carry after subtraction means “carry” or “borrow” in your specific implementation.
Mistake 5: Ignoring timing constraints in cascaded adders Each ripple stage adds ~20-25ns delay. For high-speed systems, calculate total propagation delay (N stages × per-stage delay) and verify it fits within the clock period minus setup time. For an 8-bit ripple adder at 100MHz (10ns clock): two 74HC283s ripple delay ≈ 35ns >> 10ns — will fail. Use faster logic family (74AC, 74FCT) or carry lookahead architecture.
Summary
The full adder is the complete building block of binary arithmetic: it adds three single bits (A, B, and carry-in) to produce a sum and carry-out. The SUM = A ⊕ B ⊕ C_in (three-input XOR — high for odd input count) and C_out = A·B + A·C_in + B·C_in (majority function — high when two or more inputs are high). The two-half-adder structure (HA1 on A,B; HA2 on SUM1,C_in; OR for C_out) is functionally equivalent and structurally modular.
Carry behavior divides bit positions into three types: Generate (A·B = 1 — carries regardless of C_in), Propagate (A⊕B = 1 — passes carry-in through), and Kill (both zero — absorbs carry). Generate and propagate signals are the foundation of carry lookahead, which computes all carry bits simultaneously in two gate levels — eliminating the O(N) ripple delay and enabling fast wide arithmetic.
Four standard ALU flags emerge from the adder: Carry (C4, unsigned overflow), Zero (NOR of all sum bits), Sign (MSB of result), and Overflow (XOR of carry into and out of MSB, for signed arithmetic). These flags enable all comparison operations without additional hardware.
The 74HC283 provides a complete 4-bit full adder in 16 pins; two 74HC283s cascade for 8-bit, with the 74HC182 carry lookahead unit enabling fast 16-bit operation. The adder/subtractor — XOR gates on B inputs + C_in = SUB control — handles both operations with a single circuit.
