A half adder is a combinational logic circuit that adds two single-bit binary numbers and produces two outputs: a SUM bit and a CARRY bit. Built from just two gates — an XOR gate for the sum (SUM = A ⊕ B) and an AND gate for the carry (CARRY = A · B) — the half adder is the simplest arithmetic circuit in digital electronics and the foundational building block from which all binary adders, ALUs, and computer arithmetic units are constructed.
Introduction: The Circuit That Makes Computers Count
Every computation a digital system performs — adding numbers, comparing values, encrypting data, rendering graphics, running algorithms — ultimately reduces to binary arithmetic at the hardware level. And binary arithmetic, no matter how complex, is built from one elemental operation: adding two bits together.
This elemental operation produces exactly two possible results. Zero plus zero gives zero. Zero plus one gives one. One plus zero gives one. One plus one gives two — but two in binary is written as “10,” a two-digit result. The single-digit “sum” is zero, and the overflow into the next digit position is a “carry” of one.
Two gates, two outputs. That is the entire half adder: an XOR gate computes the sum digit, an AND gate computes the carry. In the decades since this circuit was first formalized, nothing simpler has been found that does the same job, because nothing simpler can — the XOR and AND operations are the irreducible mathematical essence of binary addition.
Yet from this two-gate simplicity, remarkable things follow. Chain two half adders together with an OR gate and you get a full adder — one that can handle a carry input from the previous bit position. Chain four full adders in sequence and you have a 4-bit adder capable of adding any two 4-bit binary numbers from 0 to 15. Add control logic and you get an adder/subtractor. Add more bit width and faster carry propagation and you get the arithmetic logic unit at the heart of every processor.
The half adder is the point where abstract Boolean algebra becomes concrete arithmetic — where logic gates stop just making decisions and start doing mathematics. Understanding it completely, from the truth table derivation through the gate implementation to the multi-bit extension, builds the foundation for understanding all of digital arithmetic.
This article provides a complete treatment of the half adder: the binary addition rules that motivate its design, the truth table and Boolean derivation, the gate circuit and its implementation with real ICs, the extension to full adders and multi-bit ripple-carry adders, carry propagation delay and its implications, and a series of practical design examples that demonstrate binary addition on a breadboard and explore the adder’s role in ALU design.
Binary Addition: The Rules That Define the Circuit
Counting in Binary
Before designing the circuit, you need to understand what it computes. Binary (base-2) arithmetic uses only the digits 0 and 1. The position of each digit represents a power of 2, just as decimal positions represent powers of 10:
| Binary | Decimal |
|---|---|
| 0000 | 0 |
| 0001 | 1 |
| 0010 | 2 |
| 0011 | 3 |
| 0100 | 4 |
| 0111 | 7 |
| 1000 | 8 |
| 1111 | 15 |
| 10000 | 16 |
The rightmost bit is the least significant bit (LSB, value 2^0 = 1). Moving left, each position doubles in value: 2, 4, 8, 16, 32…
Single-Bit Addition Rules
Adding two single binary digits (A and B) follows four cases:
0 + 0 = 0 → Sum = 0, Carry = 0
0 + 1 = 1 → Sum = 1, Carry = 0
1 + 0 = 1 → Sum = 1, Carry = 0
1 + 1 = 10 (binary) → Sum = 0, Carry = 1The critical case is 1 + 1 = 10 (binary). In decimal this is 2, but in a single-bit column, the result exceeds what one bit can represent. The “0” stays in the current column (the sum) and the “1” carries over to the next more-significant column (the carry).
This carry concept is identical to decimal addition: 7 + 8 = 15 (write the 5, carry the 1 to the tens column). Binary just does this more frequently because only two values exist per digit.
The Truth Table of Addition
Organize the four cases into a truth table with two outputs:
| A | B | SUM | CARRY |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
SUM column: Compare to the XOR truth table — identical. SUM = A ⊕ B.
CARRY column: Compare to the AND truth table — identical. CARRY = A · B.
This is not a coincidence or a clever trick — it is the mathematical fact that binary addition is XOR for the same-column result and AND for the overflow. The gate circuit follows directly from this observation.
The Half Adder Circuit
Boolean Expressions
From the truth table:
SUM = A ⊕ B (Exclusive-OR)
CARRY = A · B (AND)Gate Implementation
Gate 1 — XOR gate: Inputs A and B, output SUM Gate 2 — AND gate: Inputs A and B, output CARRY
Both gates share the same two inputs. This is the complete half adder — two gates, no other components required.
┌──[XOR]──→ SUM
A, B ───┤
└──[AND]──→ CARRYVerification
Check all four input combinations against both outputs:
| A | B | XOR→SUM | AND→CARRY | Decimal check |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0+0=0 ✓ |
| 0 | 1 | 1 | 0 | 0+1=1 ✓ |
| 1 | 0 | 1 | 0 | 1+0=1 ✓ |
| 1 | 1 | 0 | 1 | 1+1=2 (10 binary) ✓ |
All four cases produce correct binary addition results.
Half Adder from NAND Gates Only
As demonstrated in Article 82, XOR can be built from four NAND gates. AND requires two NAND gates (NAND followed by NAND-as-NOT). A complete NAND-only half adder:
XOR portion (4 NAND gates):
N1 = NAND(A, B)
N2 = NAND(A, N1)
N3 = NAND(B, N1)
SUM = NAND(N2, N3)AND portion — using N1 cleverly:
Notice that N1 = NAND(A, B) = ̄(A·B). Therefore:
CARRY = A·B = NOT(N1) = NAND(N1, N1)The NAND-only half adder reuses N1:
- Gate 1: NAND(A, B) → N1
- Gate 2: NAND(A, N1) → N2
- Gate 3: NAND(B, N1) → N3
- Gate 4: NAND(N2, N3) → SUM
- Gate 5: NAND(N1, N1) → CARRY ← N1 reused!
Total: 5 NAND gates for a complete half adder — and just one IC (74HC00 quad NAND has 4 gates; need one from a second IC, or use the spare gate from a larger design).
The reuse of N1 for both SUM and CARRY computation is elegant: the NAND(A,B) result is naturally computed as an intermediate in the XOR circuit, and inverting it gives the CARRY. No redundant computation.
Practical IC Implementation
Using Dedicated ICs: 74HC86 + 74HC08
The most straightforward implementation using standard logic ICs:
Components:
- 1× 74HC86 (Quad 2-input XOR) — uses 1 of 4 gates
- 1× 74HC08 (Quad 2-input AND) — uses 1 of 4 gates
- 100nF ceramic decoupling capacitor per IC (at VCC pins)
- 5V power supply
Connections:
74HC86 pin 1 (1A) → Input A
74HC86 pin 2 (1B) → Input B
74HC86 pin 3 (1Y) → SUM output
74HC08 pin 1 (1A) → Input A
74HC08 pin 2 (1B) → Input B
74HC08 pin 3 (1Y) → CARRY output
Both ICs: Pin 14 → 5V, Pin 7 → GNDOutput indicators:
- SUM → 470Ω → LED1 → GND (lights when sum = 1)
- CARRY → 470Ω → LED2 → GND (lights when carry = 1)
Input switches:
- SPDT switch A: wiper → A input; one throw → 5V; other throw → GND
- SPDT switch B: wiper → B input; one throw → 5V; other throw → GND
Testing Procedure
- Power up the circuit (LEDs off initially with both switches at GND)
- Set A=0, B=0: Both LEDs off → SUM=0, CARRY=0 ✓
- Set A=0, B=1: SUM LED on, CARRY LED off → SUM=1, CARRY=0 ✓
- Set A=1, B=0: SUM LED on, CARRY LED off → SUM=1, CARRY=0 ✓
- Set A=1, B=1: SUM LED off, CARRY LED on → SUM=0, CARRY=1 ✓ (CARRY=1 means the result is binary “10” = decimal 2)
All four states verified. The circuit correctly implements binary addition for single-bit inputs.
Reading the Binary Output
The two outputs together represent a 2-bit binary number:
| CARRY | SUM | Binary result | Decimal |
|---|---|---|---|
| 0 | 0 | 00 | 0 |
| 0 | 1 | 01 | 1 |
| 1 | 0 | 10 | 2 |
Note: CARRY=1, SUM=1 (binary “11” = decimal 3) never occurs — the maximum result of adding two 1-bit numbers is 1+1=2, never 3. This is a fundamental limit of the half adder: its output range is 0 to 2 (two input bits summing to at most 2), which fits in two bits.
The Limitation of the Half Adder
Why “Half” Adder?
The half adder is called “half” because it can only add two bits — it has no provision for a carry-in from a less significant bit position. When adding multi-bit numbers column by column, every column except the rightmost may receive a carry from the column to its right. The half adder cannot handle this third input.
Example: Adding 1 + 1 in a multi-bit context:
0 1 1
+ 0 0 1
-------Column 0 (rightmost): 1 + 1 = 10 binary → SUM=0, CARRY=1 to column 1 Column 1: 1 + 0 + carry(1) = 10 binary → three operands! The half adder only handles two.
The solution is the full adder — a circuit with three inputs (A, B, and carry-in C_in) that produces a sum and carry-out.
The Full Adder: Completing Multi-Bit Addition
Full Adder Truth Table
A full adder adds three single bits: A, B, and carry-in C_in. Three bits summed can range from 0 to 3 (binary 11), requiring two output bits.
| A | B | C_in | SUM | C_out |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
SUM: HIGH when an ODD number of inputs are HIGH (1, or all 3). This is the three-input XOR: SUM = A ⊕ B ⊕ C_in.
C_out: HIGH when TWO OR MORE inputs are HIGH (majority of three): C_out = A·B + A·C_in + B·C_in
Deriving Full Adder from Two Half Adders
The elegant structural derivation: a full adder = two half adders + one OR gate.
Step 1 — Half adder 1: Add A and B
SUM1 = A ⊕ B
CARRY1 = A · BStep 2 — Half adder 2: Add SUM1 and C_in
SUM = SUM1 ⊕ C_in = (A ⊕ B) ⊕ C_in = A ⊕ B ⊕ C_in ✓
CARRY2 = SUM1 · C_in = (A ⊕ B) · C_inStep 3 — OR gate for carry-out:
C_out = CARRY1 + CARRY2 = A·B + (A⊕B)·C_inProof that this equals the full adder C_out:
A·B + (A⊕B)·C_in
= A·B + (Ā·B + A·B̄)·C_in
= A·B + Ā·B·C_in + A·B̄·C_inNow expand the full adder C_out: A·B + A·C_in + B·C_in:
A·B + A·C_in + B·C_in
= A·B + A·C_in·(B+B̄) + B·C_in·(A+Ā)
= A·B + A·B·C_in + A·B̄·C_in + A·B·C_in + Ā·B·C_in
= A·B·(1 + C_in + C_in) + A·B̄·C_in + Ā·B·C_in
= A·B + A·B̄·C_in + Ā·B·C_in ✓ (same expression)The two-half-adder structure correctly implements the full adder carry-out.
Full Adder Gate Circuit
Components:
- 2× XOR gates (SUM1 and SUM)
- 2× AND gates (CARRY1 and CARRY2)
- 1× OR gate (C_out)
Total: 5 gates for one full adder.
Connections:
XOR1: A, B → SUM1
AND1: A, B → CARRY1
XOR2: SUM1, C_in → SUM (final)
AND2: SUM1, C_in → CARRY2
OR: CARRY1, CARRY2 → C_outICs for one full adder:
- 74HC86 (quad XOR) — uses 2 of 4 gates
- 74HC08 (quad AND) — uses 2 of 4 gates
- 74HC32 (quad OR) — uses 1 of 4 gates
Three ICs for one full adder — generous with gate count. Alternatively, build from NAND gates only (9 NAND gates) for single-IC-family designs.
Full Adder from NAND Gates Only
The most efficient NAND implementation uses 9 NAND gates. Using the XOR-from-4-NAND structure plus NAND for carry logic:
N1 = NAND(A, B) → ̄(A·B)
N2 = NAND(A, N1) → used for SUM1 XOR
N3 = NAND(B, N1) → used for SUM1 XOR
SUM1 = NAND(N2, N3) → A ⊕ B [XOR1: gates 1-4]
N5 = NAND(SUM1, C_in) → ̄(SUM1·C_in)
N6 = NAND(SUM1, N5) → used for SUM XOR
N7 = NAND(C_in, N5) → used for SUM XOR
SUM = NAND(N6, N7) → SUM1 ⊕ C_in = A⊕B⊕C_in [XOR2: gates 5-8]
C_out = NAND(N1, N5) → ̄(̄(A·B) · ̄((A⊕B)·C_in))
= A·B + (A⊕B)·C_in [gate 9]9 NAND gates total. The carry-out uses N1 and N5 — intermediate results already computed for the XOR stages. No redundant computation.
IC implementation: One 74HC00 (4 NAND) + one 74HC10 (3× 3-input, but we need 2-input only) — actually use two 74HC00 packages (8 gates each = 16 gates, 9 used, 7 spare) for a complete NAND-only full adder.
The 4-Bit Ripple-Carry Adder
Architecture
Four full adders chained together, with carry-out of each feeding carry-in of the next:
A3B3 A2B2 A1B1 A0B0
↓↓ ↓↓ ↓↓ ↓↓
0 → [FA3] → [FA2] → [FA1] → [FA0]→
↓ ↓ ↓ ↓
S3 S2 S1 S0
↓
C_out (overflow)- FA0 (rightmost): adds A0, B0, carry-in = 0. Produces S0 and carry to FA1.
- FA1: adds A1, B1, carry from FA0. Produces S1 and carry to FA2.
- FA2: adds A2, B2, carry from FA1. Produces S2 and carry to FA3.
- FA3 (leftmost): adds A3, B3, carry from FA2. Produces S3 and carry-out (overflow flag).
Example: Adding 6 + 11 = 17
A = 0110 (decimal 6)
B = 1011 (decimal 11)Bit 0 (FA0): A0=0, B0=1, C_in=0 → SUM=1, C_out=0 Bit 1 (FA1): A1=1, B1=1, C_in=0 → SUM=0, C_out=1 Bit 2 (FA2): A2=1, B2=0, C_in=1 → SUM=0, C_out=1 Bit 3 (FA3): A3=0, B3=1, C_in=1 → SUM=0, C_out=1
Result:
- S3 S2 S1 S0 = 0001
- C_out = 1 (overflow — result exceeds 4 bits!)
Full result = 1 0001 binary = 17 decimal ✓ (C_out is the 5th bit)
Example: Adding 5 + 9 = 14 (fits in 4 bits)
A = 0101 (decimal 5)
B = 1001 (decimal 9)Bit 0: A0=1, B0=1, C_in=0 → SUM=0, C_out=1 Bit 1: A1=0, B1=0, C_in=1 → SUM=1, C_out=0 Bit 2: A2=1, B2=0, C_in=0 → SUM=1, C_out=0 Bit 3: A3=0, B3=1, C_in=0 → SUM=1, C_out=0
Result: S3 S2 S1 S0 = 1110, C_out = 0 Binary 1110 = decimal 14 ✓
Overflow Detection
When adding two N-bit unsigned numbers, C_out=1 indicates the result exceeds N bits (overflow). For unsigned arithmetic, C_out is the carry flag.
For signed (two’s complement) arithmetic, overflow is different: it occurs when adding two positive numbers gives a negative result (or two negatives give positive). Signed overflow detection:
OVERFLOW = C_out_bit_N XOR C_out_bit_{N-1}This XOR of the final two carry bits detects signed overflow — standard in all processors.
The 74HC283: 4-Bit Adder in a Single IC
The 74HC283 is a dedicated 4-bit binary full adder in a 16-pin DIP/SOIC:
- Inputs: A3-A0, B3-B0, C0 (carry-in)
- Outputs: S3-S0, C4 (carry-out)
- Supply: 2V–6V
- Propagation delay (sum): ~20ns at 5V
- Propagation delay (carry): ~15ns at 5V (faster for carry, since it affects the next stage)
Using two 74HC283s for 8-bit addition:
- IC1: adds A3-A0 + B3-B0, C0=0, produces S3-S0 and C4
- IC2: adds A7-A4 + B7-B4, C0=IC1_C4 (carry from lower byte), produces S7-S4 and C4
Two ICs, 16-pin packages each — an 8-bit adder consuming minimal board space.
Pin connections for 74HC283:
- Pins 5,3,14,12 (A4,A3,A2,A1 in datasheet notation — confusingly numbered)
- Pins 6,2,15,11 (B4,B3,B2,B1)
- Pin 7: C0 (carry-in)
- Pins 9,1,13,4 (S4,S3,S2,S1 — sum outputs)
- Pin 9: C4 (carry-out, which is actually the 5th bit output)
- Pins 8,16: GND, VCC
Note: The 74HC283 pin numbering uses 1-indexed A1-A4 and B1-B4 rather than 0-indexed A0-A3/B0-B3. Pin 1 corresponds to the A1 (LSB), pin 5 to A4 (MSB). Always check the datasheet carefully.
Ripple-Carry Delay: The Speed Limitation
Why Ripple Adders Are Slow
In a ripple-carry adder, the carry signal must propagate from bit 0 to bit N before the final sum is valid. Each full adder introduces a carry propagation delay of approximately one gate level (since C_out depends on the carry computation path). For N-bit addition:
Worst-case carry propagation delay:
t_carry_total = N × t_carry_per_stageFor a 74HC283 (t_carry ≈ 15ns per stage) in a 32-bit ripple chain (eight 74HC283s):
t_total = 8 × 15ns = 120ns
Maximum addition rate = 1 / 120ns ≈ 8.3 MHzA 100MHz processor cannot use a 32-bit ripple-carry adder — it would need to wait 12+ clock cycles for the addition to complete.
Carry Lookahead: The Speed Solution
Carry-lookahead adders (CLA) compute all carry bits simultaneously from the original inputs, eliminating the ripple propagation chain. Two signals per bit position enable this:
Generate: G_i = A_i · B_i (this bit generates a carry regardless of carry-in) Propagate: P_i = A_i ⊕ B_i (this bit propagates a carry-in to carry-out)
The carry into each bit position can be computed directly:
C1 = G0 + P0·C0
C2 = G1 + P1·C1 = G1 + P1·G0 + P1·P0·C0
C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0
C4 = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0 + P3·P2·P1·P0·C0All carry bits are computed in just two gate levels (one AND level for the product terms, one OR level to sum them) regardless of the number of bits. A 32-bit CLA adder has the same propagation delay as a 4-bit CLA adder — effectively O(1) delay rather than O(N).
The trade-off: CLA requires many more gates. The carry logic for a 4-bit CLA uses 4 AND gates and 4 OR gates (of increasing input counts) versus just the cascade carry in ripple. For modern VLSI, the extra gates are acceptable for the speed gain.
Modern Adder Architectures
Real processors use more sophisticated adder designs:
Carry-select adder: Compute two copies of the upper half in parallel (one assuming carry-in=0, one assuming carry-in=1), then select the correct result once the lower half’s actual carry is known. Reduces delay to approximately O(√N).
Prefix adders (Kogge-Stone, Brent-Kung): Use a tree structure to compute generates and propagates across all bit positions in O(log N) time. Used in high-performance processor designs.
The fundamental insight: All these adder types use the same bit-level XOR and AND operations as the half adder — only the carry propagation strategy differs. The half adder is still the atomic unit; the architecture determines how carries flow between those atomic units.
Complete Design Example 1: 2-Bit Adder on Breadboard
Application: Build a circuit that adds two 2-bit binary numbers (A1A0 and B1B0) and displays the 3-bit result (S2 S1 S0) on three LEDs. Demonstrate all 16 addition combinations (0+0 through 3+3).
Range: 2-bit numbers range from 0 to 3. Maximum sum: 3+3=6 (binary 110), requiring 3 output bits.
Circuit design:
Bit 0 (half adder — no carry-in):
- XOR gate 1: A0, B0 → S0
- AND gate 1: A0, B0 → C01 (carry from bit 0 to bit 1)
Bit 1 (full adder — carry-in from bit 0):
- XOR gate 2: A1, B1 → TEMP1
- XOR gate 3: TEMP1, C01 → S1
- AND gate 2: A1, B1 → C_and1
- AND gate 3: TEMP1, C01 → C_and2
- OR gate 1: C_and1, C_and2 → S2 (carry-out = MSB of result)
Total gates: 3 XOR + 3 AND + 1 OR = 7 gates
ICs:
- 74HC86 (quad XOR): uses gates 1, 2, 3 — all used
- 74HC08 (quad AND): uses gates 1, 2, 3 — one spare
- 74HC32 (quad OR): uses gate 1 — three spare
Switches: 4 SPDT switches (A1, A0, B1, B0) LEDs: 3 LEDs with 470Ω resistors (S2, S1, S0)
Testing — add 2 + 3:
A = 10 (binary 2), B = 11 (binary 3)
A1=1, A0=0, B1=1, B0=1Bit 0: A0=0, B0=1 → S0=1, C01=0 Bit 1: A1=1, B1=1, C01=0
- TEMP1 = 1⊕1 = 0
- S1 = 0⊕0 = 0
- C_and1 = 1·1 = 1
- C_and2 = 0·0 = 0
- S2 = 1+0 = 1
Result: S2 S1 S0 = 101 = decimal 5 ✓ (2+3=5)
All 16 combinations to verify:
| A1 | A0 | B1 | B0 | A | B | S2 | S1 | S0 | Sum |
|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 ✓ |
| 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 ✓ |
| 0 | 1 | 1 | 0 | 1 | 2 | 0 | 1 | 1 | 3 ✓ |
| 1 | 0 | 1 | 0 | 2 | 2 | 1 | 0 | 0 | 4 ✓ |
| 1 | 1 | 1 | 1 | 3 | 3 | 1 | 1 | 0 | 6 ✓ |
Complete Design Example 2: 4-Bit Adder Using 74HC283
Application: Build a 4-bit binary adder using a single 74HC283 IC. Display the 5-bit result (4 sum bits + carry-out) on five LEDs. Add manual inputs via DIP switches.
Components:
- 1× 74HC283 (4-bit full adder)
- 8× SPDT DIP switches (A3-A0, B3-B0)
- 5× LEDs + 5× 470Ω resistors (S3-S0, C4)
- 100nF decoupling capacitor
- 5V supply
Connections:
74HC283:
A4(pin 5)=A3, A3(pin 3)=A2, A2(pin 14)=A1, A1(pin 12)=A0
B4(pin 6)=B3, B3(pin 2)=B2, B2(pin 15)=B1, B1(pin 11)=B0
C0(pin 7) = GND (no carry-in for fresh addition)
S4(pin 9)→LED_S3, S3(pin 1)→LED_S2, S2(pin 13)→LED_S1, S1(pin 4)→LED_S0
C4(pin 9)... Wait — the 74HC283 actually has carry-out at pin 9 and the sum outputs at pins 4, 1, 13, 10. Let me use the actual datasheet pinout:
74HC283 actual pin assignment:
- Pin 5: A4 (MSB A input)
- Pin 3: A3
- Pin 14: A2
- Pin 12: A1 (LSB A input)
- Pin 6: B4 (MSB B input)
- Pin 2: B3
- Pin 15: B2
- Pin 11: B1 (LSB B input)
- Pin 7: C0 (carry-in)
- Pin 9: S4 (MSB sum / carry-out of 4-bit add) — actually this is C4
- Pin 10: S4 sum bit
- Pin 1: S3
- Pin 13: S2
- Pin 4: S1 (LSB sum)
- Pin 16: VCC
- Pin 8: GND
Simplified wiring for 4-bit add (A + B, 0-indexed internally as 1-4):
Connect A inputs to 4 switches (A side). Connect B inputs to 4 switches (B side). C0 (carry-in) tied to GND. Sum outputs S1-S4 drive 4 LEDs. C4 drives 1 LED (overflow indicator).
Test: 7 + 9 = 16
A = 0111 (7): A4=0, A3=1, A2=1, A1=1
B = 1001 (9): B4=1, B3=0, B2=0, B1=1
Expected: sum=16 = 10000 binary → S4-S1=0000, C4=1LED pattern: four sum LEDs off, overflow LED on → displays C4=1, S=0000 representing 1_0000 = 16 ✓
Test: 5 + 6 = 11
A = 0101 (5), B = 0110 (6)
Expected: 1011 binary, C4=0LEDs: C4 off, S4=1, S3=0, S2=1, S1=1 → 1011 = 11 ✓
Complete Design Example 3: Binary Adder/Subtractor
Application: Extend the 74HC283 adder to perform both addition and subtraction using a single control line (SUB). When SUB=0: result = A + B. When SUB=1: result = A – B.
Principle: Two’s complement subtraction: A – B = A + (̄B) + 1
- Invert all B bits: use XOR gates (B_i ⊕ SUB → inverts when SUB=1, passes when SUB=0)
- Add 1: use the carry-in C0 (set C0 = SUB → adds 1 when subtracting)
Circuit additions:
- 4× XOR gates (one per B bit): B_effective[i] = B[i] ⊕ SUB
- Connect SUB to C0 (carry-in) of 74HC283
- Connect B_effective inputs to the 74HC283 B inputs instead of direct B
Gate implementation:
- 4× XOR from 74HC86 (quad XOR): inputs B[i] and SUB, outputs B_effective[i]
- Connect SUB signal to 74HC283 pin 7 (C0)
- A inputs unchanged
Total additional ICs: One 74HC86 (uses 4 gates — all of them)
Test: 9 – 5 = 4
A = 1001 (9), B = 0101 (5), SUB=1
B_effective = B ⊕ 1111 = 1010 (inverted)
C0 = 1
74HC283 computes: 1001 + 1010 + 1 = 10100
Result (lower 4 bits): 0100 = 4, C4=1 (ignore overflow for same-sign subtraction)✓ 9 – 5 = 4 correctly computed.
Test: 3 – 7 = -4 (two’s complement result)
A = 0011 (3), B = 0111 (7), SUB=1
B_effective = 1000 (inverted)
C0 = 1
3 + 8 + 1 = 12 = 1100 binary, C4=0Result = 1100 binary. In two’s complement: 1100 = -4 (invert 0100, add 1 = 0100+1=… wait: -(1100) = 0011+1 = 0100 = 4, so 1100 = -4) ✓
The same circuit adds and subtracts — SUB=0 for add, SUB=1 for subtract. This is exactly how the ALU in every processor implements both operations with a single adder circuit.
Complete Design Example 4: BCD Adder (Binary-Coded Decimal)
Application: Add two BCD digits (0-9) and produce a valid BCD result with carry. BCD stores each decimal digit as a 4-bit binary code (0=0000 through 9=1001). The result of adding two BCD digits must be a valid BCD digit or valid BCD pair (for carry).
The BCD correction problem: Standard binary addition: 5+8 = 0101+1000 = 1101 = 13 decimal. But 1101 in BCD is invalid (no digit 13). BCD result should be: 1 (carry), 3 (digit) → 0001_0011.
Binary sums 0-9 need no correction. Sums 10-15 need +6 correction (to skip the invalid hex digits A-F) and generate a carry:
If SUM > 9 (or C_out=1): BCD_result = SUM + 6, carry_out = 1
Else: BCD_result = SUM, carry_out = 0BCD correction detection: A correction is needed when the 4-bit sum exceeds 9. The condition:
CORRECT = C4 + (S3·S2) + (S3·S1)Where S3-S0 are the sum bits and C4 is the carry from the 4-bit adder.
- C4=1: sum ≥ 16, always needs correction
- S3·S2=1: sum ≥ 12 (1100+) if S3=1 and S2=1, sum is at least 12
- S3·S1=1: sum ≥ 10 if S3=1 and S1=1 (values 10,11)
Implementation:
- Stage 1: 74HC283 adds the two BCD digits normally
- Detection: AND gates compute S3·S2 and S3·S1; OR gate combines with C4 → CORRECT signal
- Stage 2: Second 74HC283 adds 6 (0110) when CORRECT=1; adds 0 when CORRECT=0 Implement by: connect CORRECT to the B2 and B1 inputs of the second adder (B2=CORRECT, B1=CORRECT forms 0110 when both = CORRECT=1, and 0000 when CORRECT=0) Wait: 6 = 0110, so B3=0, B2=CORRECT, B1=CORRECT, B0=0
- The CORRECT signal also becomes the BCD carry-out
Final carry-out:
BCD_CARRY = CORRECT (from stage 1)
BCD_SUM = output of stage 2 adderGate total: 2× 74HC283 + partial 74HC08 (for AND gates) + partial 74HC32 (for OR). The 74HC4518 is a dedicated dual BCD counter that uses this exact correction internally.
Half Adder in Context: The Building Block of ALUs
What Is an ALU?
The Arithmetic Logic Unit (ALU) is the component in a processor that performs arithmetic (addition, subtraction) and logical (AND, OR, XOR, NOT) operations. At its core is a parallel array of full adders — one per bit width. A 64-bit ALU has 64 full adders arranged in a tree with fast carry lookahead logic.
The half adder’s direct descendants in a modern processor:
- Half adder (2 gates): Single-bit addition, no carry-in
- Full adder (5 gates): Single-bit addition with carry-in
- 4-bit ripple adder (4× full adders): 4-bit addition
- 4-bit CLA adder: 4-bit addition, faster carry
- 64-bit prefix adder (Kogge-Stone): 64-bit addition in O(log 64) = 6 gate levels
- ALU slice: Adder + multiplexer for operation selection + flag generation
- Full ALU: Multiple ALU slices + forwarding + bypass logic
Every single one of these is built from XOR gates (for sum bits) and AND/OR gates (for carry bits) — the same two gates as the half adder, scaled and optimized.
From Half Adder to Multiplication
Binary multiplication (like decimal multiplication) is performed by shifting and adding:
A × B = A × (B3·2³ + B2·2² + B1·2¹ + B0·2⁰)
= A·B3·8 + A·B2·4 + A·B1·2 + A·B0·1Each partial product A·Bi is computed by AND’ing each bit of A with Bi:
- A3Bi, A2Bi, A1Bi, A0Bi — four AND gates per partial product
The partial products are then summed using a tree of adders. A 4×4 multiplier uses 16 AND gates (for partial products) and a series of full adders and half adders to sum them. A modern processor uses hundreds of adders in a Wallace tree or Dadda multiplier structure to multiply 64-bit numbers in a few clock cycles.
Even complex mathematical functions (sine, cosine, logarithm, square root) are ultimately computed by sequences of additions and multiplications — all reducible to XOR and AND at the gate level.
Common Design Mistakes and How to Avoid Them
Mistake 1: Using a half adder where a full adder is needed In multi-bit adders, every bit position except the LSB may receive a carry-in. Using a half adder (no carry-in) for any position other than bit 0 produces incorrect results for any input combination that generates a carry into that position. Always use full adders for all bit positions except the rightmost.
Mistake 2: Floating the carry-in of the LSB full adder When cascading full adder ICs (like 74HC283), the carry-in (C0) of the least significant stage must be tied to GND (for addition) or to the SUB control signal (for subtraction). A floating carry-in produces unpredictable results — it may settle HIGH or LOW depending on noise, causing random addition errors.
Mistake 3: Ignoring the carry-out flag Adding two 4-bit numbers can produce a 5-bit result. Ignoring the carry-out (C4) means results like 12+7=19 display as 3 (only the lower 4 bits). Always connect C_out to an overflow indicator or to the carry-in of the next higher-order adder stage.
Mistake 4: Confusing 74HC283 pin numbering The 74HC283 uses 1-indexed pin names (A1-A4, B1-B4, S1-S4) where A1/B1/S1 are the LSB pins. This is the opposite of the common 0-indexed convention used in most digital design explanations. Always verify: connect the LSB inputs/outputs to the pins numbered 1, not 4.
Mistake 5: Propagation delay in cascaded adders When cascading multiple 74HC283s for wider addition, the total delay is the sum of carry propagation delays through all stages. At 100MHz clock, the sum of two 8-bit numbers (two 74HC283s in ripple cascade, ~30ns total carry propagation) may not settle before the next clock edge. Add pipeline registers or use faster adder architecture for high-speed applications.
Summary
The half adder is the simplest arithmetic circuit: an XOR gate for the sum bit and an AND gate for the carry, directly implementing the four cases of single-bit binary addition. Its simplicity is its elegance — the Boolean operations XOR and AND are the exact mathematical representation of binary addition’s sum and carry.
The half adder’s single limitation — no carry-in — is solved by the full adder: two half adders plus an OR gate for the carry-out, adding three single bits (A, B, and carry-in from the previous position). Four full adders chained together form a 4-bit ripple-carry adder; the 74HC283 implements this in a single 16-pin IC.
Ripple-carry adders are limited by carry propagation time (O(N) delay). Carry-lookahead adders eliminate this by computing all carries simultaneously from generate and propagate signals, reducing delay to O(log N). Modern processors use prefix adder architectures for 64-bit addition in approximately 6 gate levels — but the bit-level operation remains XOR for sum and AND/OR for carry, unchanged from the half adder.
The adder/subtractor circuit — XOR gates on B inputs controlled by a SUB line, with SUB connected to carry-in — adds and subtracts with identical hardware by exploiting two’s complement arithmetic. This pattern appears in every processor ALU ever built.
