An SR latch is the simplest digital memory circuit, built from two cross-coupled NOR or NAND gates with Set (S) and Reset (R) control inputs. In the hold state (S=R=0 for NOR, S̄=R̄=1 for NAND), the latch maintains its current Q output indefinitely without any external power or refresh. Asserting S drives Q to 1 (set), asserting R drives Q to 0 (reset), and the forbidden state (both S and R simultaneously asserted) produces undefined behavior. SR latches are the foundational memory element from which all flip-flops, registers, and RAM are derived.
Introduction: Where Memory Begins
Every digital system that does anything useful over time needs some form of memory. The simplest possible form — storing exactly one bit, indefinitely, with two control inputs — is the SR latch. It does not use a clock, it does not require refresh, and it does not have the complexity of edge triggering or master-slave configurations. Two gates, four wires, and you have the most elementary memory element in all of digital electronics.
The SR latch’s simplicity makes it the ideal starting point for understanding how memory works at the circuit level. In Article 85, flip-flops were introduced conceptually, with SR latches mentioned as the base from which more complex types are built. This article goes deeper: deriving the SR latch’s behavior from first principles, analyzing every input combination including the subtle dynamics of the forbidden state, examining both the NOR and NAND implementations with their important differences, working through the timing analysis that determines how fast the latch can operate reliably, and building four complete practical circuits that use SR latches in real applications.
Understanding the SR latch thoroughly also illuminates the behavior of every more complex flip-flop: the D latch is an SR latch with added input logic; the edge-triggered D flip-flop is two gated SR latches in master-slave configuration; the JK flip-flop adds feedback around an SR latch to handle the forbidden state. Every time you use a 74HC74, a 74HC175, or a flip-flop inside an FPGA, the physical transistors at the core implement the same cross-coupled feedback that defines the SR latch. Mastering the SR latch means mastering the foundation of all sequential digital circuits.
The Bistable Core: Why Two Gates Can Store a Bit
Starting From Cross-Coupled Inverters
Before examining the SR latch with its control inputs, consider the simpler question: what is the minimum circuit that can stably hold either Q=0 or Q=1?
Two inverters connected in a loop:
NOT gate 1: input = X, output = Y
NOT gate 2: input = Y, output = XCheck the stable states:
- If X=0: Gate 1 output Y=1. Gate 2 input=1, output=0=X. ✓ Self-consistent, stable.
- If X=1: Gate 1 output Y=0. Gate 2 input=0, output=1=X. ✓ Self-consistent, stable.
Both states are stable — the circuit holds whichever state it enters. This is bistability from positive feedback: the output of each gate feeds back to reinforce the current state rather than oppose it.
The problem is that there are no inputs. Once the circuit settles at power-up (randomly, to whichever state the transistors happen to favor), it stays there forever. To be useful as memory, the circuit needs a way to deliberately force it into either state on demand.
Why NOR Gates (Not Inverters) Enable Controlled Memory
NOR gates are inverters with an extra input: NOR(A, B) = NOT(A OR B). When that extra input is 0, the NOR gate behaves exactly as an inverter: NOR(A, 0) = NOT A. This means a NOR SR latch in the hold state (both control inputs = 0) behaves exactly like the cross-coupled inverter pair — perfectly stable bistability.
When one control input is asserted HIGH, it overrides the feedback: NOR(A, 1) = 0 regardless of A. This forced output breaks the existing feedback state and drives the latch to a new stable state.
The elegance of the NOR SR latch is that the same gate that maintains bistability (by acting as an inverter when its control input is 0) also provides the mechanism to change state (by forcing its output when its control input is 1). There are no separate “memory” and “control” circuits — they share the same two gates.
The NOR SR Latch: Complete Analysis
Circuit Structure
Two NOR gates, cross-coupled:
S ──┐ ┌── R
NOR1 ──── Q Q̄ ──── NOR2
Q̄ ──┘ └── Q
(feedback) (feedback)More precisely:
- NOR Gate 1: inputs = {S, Q̄_feedback}, output = Q
- NOR Gate 2: inputs = {R, Q_feedback}, output = Q̄
Where Q̄_feedback is the output of Gate 2 fed back to Gate 1’s input, and Q_feedback is Gate 1’s output fed back to Gate 2’s input.
Gate equations:
Q = NOR(S, Q̄) = ̄(S + Q̄)
Q̄ = NOR(R, Q) = ̄(R + Q)Analyzing All Four Input States
State 1: S=0, R=0 — Hold (Memory)
With both control inputs LOW, the NOR gates reduce to inverters:
Q = NOR(0, Q̄) = ̄Q̄ = Q (inverter of inverter = original value)
Q̄ = NOR(0, Q) = ̄Q (inverter)The circuit is self-consistent for any Q value. If Q=1: NOR(0,0)=1 ✓, NOR(0,1)=0 ✓. If Q=0: NOR(0,1)=0 ✓, NOR(0,0)=1 ✓. Both states are stable — the latch holds whatever value it currently has.
Key insight: The latch remembers because the feedback loop sustains the current state. Q=1 keeps Gate 2 output LOW, which keeps Gate 1 output HIGH (Q=1). Q=0 keeps Gate 1 output LOW, which keeps Gate 2 output HIGH. Each state is self-reinforcing.
State 2: S=1, R=0 — Set (Q→1)
With S=1, Gate 1 is overridden:
Q = NOR(S=1, Q̄) = NOR(1, anything) = 0Wait — this gives Q=0, not Q=1. This appears to contradict “S sets Q to 1.” Let me re-examine which gate S connects to.
Recall from the careful analysis in Article 85: S connects to the gate whose output is Q̄, not Q.
Corrected wiring:
- Gate 1 (G1): inputs = {S, Q_feedback}, output = Q̄
- Gate 2 (G2): inputs = {R, Q̄_feedback}, output = Q
So:
Q̄ = NOR(S, Q) [Gate 1]
Q = NOR(R, Q̄) [Gate 2]With S=1, R=0:
- G1: Q̄ = NOR(1, Q) = 0 regardless of Q → Q̄=0
- G2: Q = NOR(0, Q̄=0) = NOR(0,0) = 1 → Q=1 ✓
The Set operation works: S=1 forces Q̄=0, which in turn forces Q=1 through Gate 2.
State 3: S=0, R=1 — Reset (Q→0)
With R=1:
- G2: Q = NOR(1, Q̄) = 0 regardless of Q̄ → Q=0
- G1: Q̄ = NOR(0, Q=0) = NOR(0,0) = 1 → Q̄=1 ✓
Reset works: R=1 forces Q=0, which forces Q̄=1.
State 4: S=1, R=1 — Forbidden
Both S=1 and R=1 simultaneously:
- G1: Q̄ = NOR(1, Q) = 0 regardless → Q̄=0
- G2: Q = NOR(1, Q̄) = 0 regardless → Q=0
Both Q and Q̄ equal 0 simultaneously. This violates the fundamental relationship Q̄ = NOT Q. The circuit is in an internally inconsistent state.
While stable during the forbidden input state (both gates satisfied with their outputs), the critical problem occurs when S and R simultaneously return to 0. The behavior when this happens requires dynamic analysis — covered in the forbidden state section below.
Complete NOR SR Latch Truth Table
| S | R | Q_next | Q̄_next | State |
|---|---|---|---|---|
| 0 | 0 | Q_prev | Q̄_prev | Hold (memory) |
| 0 | 1 | 0 | 1 | Reset (Q→0) |
| 1 | 0 | 1 | 0 | Set (Q→1) |
| 1 | 1 | 0* | 0* | Forbidden |
*Both outputs 0 simultaneously while inputs remain at S=R=1. Output undefined when inputs return to 0.
Characteristic Equation
The SR latch’s next-state behavior can be expressed as a characteristic equation:
Q_next = S + ̄R · Q_prev (when SR ≠ 1)Read: Q goes HIGH if S is asserted, stays HIGH if R is not asserted and Q was HIGH, otherwise LOW.
Verification:
- S=1, R=0: Q_next = 1 + 1·Q_prev = 1 ✓
- S=0, R=1: Q_next = 0 + 0·Q_prev = 0 ✓
- S=0, R=0: Q_next = 0 + 1·Q_prev = Q_prev ✓
The NAND SR Latch: Active-LOW Inputs
Why NAND Gates Work
NAND gates have the complementary property to NOR: NAND(A, 0) = 1 regardless of A, and NAND(A, 1) = NOT A. So:
- When control input = 1 (inactive): NAND acts as an inverter → maintains bistability
- When control input = 0 (active): NAND outputs 1 regardless → overrides feedback
This means the NAND SR latch has active-LOW inputs — the control inputs are active when LOW, not when HIGH.
NAND SR Latch Circuit
S̄ ──┐ ┌── R̄
NAND1 ──── Q Q̄ ──── NAND2
Q̄ ──┘ └── Q
(feedback) (feedback)Gate equations (using the same wiring convention as NOR, with S̄ and R̄ designating active-LOW):
- NAND Gate 1: inputs = {S̄, Q̄_feedback}, output = Q
- NAND Gate 2: inputs = {R̄, Q_feedback}, output = Q̄
Q = NAND(S̄, Q̄)
Q̄ = NAND(R̄, Q)NAND SR Latch Truth Table
| S̄ | R̄ | Q_next | Q̄_next | State |
|---|---|---|---|---|
| 1 | 1 | Q_prev | Q̄_prev | Hold (memory) |
| 0 | 1 | 1 | 0 | Set (Q→1, active-LOW) |
| 1 | 0 | 0 | 1 | Reset (Q→0, active-LOW) |
| 0 | 0 | 1* | 1* | Forbidden |
*Both outputs HIGH simultaneously while inputs remain at S̄=R̄=0.
State Analysis
Hold (S̄=1, R̄=1):
Q = NAND(1, Q̄) = NOT Q̄ = Q (NAND with 1 = inverter)
Q̄ = NAND(1, Q) = NOT Q = Q̄Self-consistent, holds both stable states. ✓
Set (S̄=0, R̄=1):
With S̄=0 on Gate 1:
Q = NAND(S̄=0, Q̄) = NAND(0, anything) = 1 → Q=1
Q̄ = NAND(R̄=1, Q=1) = NAND(1,1) = 0 → Q̄=0 ✓S̄=0 forces Q=1 directly. ✓
Reset (S̄=1, R̄=0):
Q̄ = NAND(R̄=0, Q) = 1 → Q̄=1
Q = NAND(S̄=1, Q̄=1) = NAND(1,1) = 0 → Q=0 ✓Forbidden (S̄=0, R̄=0):
Q = NAND(0, Q̄) = 1 (regardless)
Q̄ = NAND(0, Q) = 1 (regardless)Both outputs HIGH — violates Q̄=NOT Q.
Key Differences: NOR vs. NAND SR Latch
| Property | NOR SR Latch | NAND SR Latch |
|---|---|---|
| Active control level | HIGH (S=1, R=1) | LOW (S̄=0, R̄=0) |
| Hold state inputs | S=0, R=0 | S̄=1, R̄=1 |
| Forbidden state inputs | S=1, R=1 | S̄=0, R̄=0 |
| Forbidden output | Both Q=Q̄=0 | Both Q=Q̄=1 |
| Gate output when active | LOW (NOR forces 0) | HIGH (NAND forces 1) |
| Common IC | 74HC02 (NOR) | 74HC00 (NAND) |
| Switch debounce | Less common | Standard (SPDT switches pull LOW) |
The NAND SR latch is more commonly used in practice because:
- NAND gates are faster and more widely available in CMOS
- SPDT switch debounce circuits naturally produce active-LOW signals (switches pull to ground)
- The forbidden condition (both inputs LOW) is less likely to occur accidentally with pull-up resistors (resistors pull lines HIGH by default — the safe hold state)
The Forbidden State: Dynamic Analysis
What Happens When S and R Return to Hold Simultaneously
The forbidden state is stable while both control inputs are asserted — both outputs remain at their forced values (0 for NOR, 1 for NAND). The critical problem occurs at the transition back to the hold state.
For NOR SR latch, S=R=1 → S=R=0 simultaneously:
Immediately after S and R return to 0, both gates are computing:
Q = NOR(0, Q̄=0) = NOR(0,0) = 1
Q̄ = NOR(0, Q=0) = NOR(0,0) = 1Both gates want to output 1. This is self-consistent temporarily: both outputs are 1, and both gates see inputs (0,1) — wait:
With Q=1 and Q̄=1:
Q = NOR(0, Q̄=1) = NOR(0,1) = 0
Q̄ = NOR(0, Q=1) = NOR(0,1) = 0Now both want to output 0 again. With Q=0 and Q̄=0:
Q = NOR(0, Q̄=0) = 1
Q̄ = NOR(0, Q=0) = 1The circuit oscillates between (1,1) and (0,0) — each state immediately implies the other. This is an unstable equilibrium: in an ideal circuit, it would oscillate indefinitely. In a real CMOS circuit, tiny differences in transistor parameters, power supply noise, and thermal fluctuations break the symmetry. The circuit eventually resolves to either Q=0,Q̄=1 or Q=1,Q̄=0 — but which one is determined by unpredictable physical noise, not by any controllable input.
Metastability: The Deeper Problem
The transition out of the forbidden state passes through a metastable region — an unstable equilibrium point where Q≈Q̄≈V_DD/2 (approximately half the supply voltage). In this region, the regenerative feedback that normally drives the latch quickly to a valid state is nearly zero. The circuit may remain near the metastable point for a statistically distributed amount of time before resolving.
Resolution time distribution: The probability that the latch is still metastable after time τ from the forbidden-to-hold transition is:
P(metastable after τ) ≈ exp(-τ / t_c)Where t_c is a time constant characteristic of the latch’s analog behavior (related to the gain-bandwidth product of the feedback loop). For 74HC gates, t_c ≈ 0.5–1ns. The probability drops exponentially — after 5×t_c ≈ 5ns, metastability probability is e^(-5) ≈ 0.7%. After 20ns, it is negligible.
Why metastability matters even briefly: If subsequent logic samples Q before it resolves to a valid level, that logic may itself enter a metastable or incorrect state. In a synchronous system where Q feeds into a clock input, the entire downstream circuit produces unpredictable results.
Practical rule: Never apply simultaneous S=R=1 (for NOR) or S̄=R̄=0 (for NAND) and never allow both to return to inactive simultaneously. Circuit design must guarantee this condition never occurs. The D latch and D flip-flop eliminate the forbidden state entirely by making S and R structurally complementary.
Timing Requirements for Reliable Latch Operation
For reliable set or reset operation, the active input must be held long enough for the latch to complete its state transition — called the pulse width minimum (t_W):
For NOR SR latch: S (or R) must be HIGH for at least t_W_min.
The state transition requires:
- Gate 1 output to change (propagation delay t_pd1)
- Gate 2 to see new feedback and update (propagation delay t_pd2)
- Gate 1 to see new feedback from Gate 2 (confirming stable state)
Minimum pulse width:
t_W_min ≈ 2 × t_pd (two gate propagation delays)For 74HC gates (t_pd ≈ 7ns): t_W_min ≈ 14ns.
Any S pulse shorter than 14ns may not fully establish the new state before S returns to 0. The latch may return to its previous state or enter a metastable condition.
For the 74HC279 (quad NAND SR latch): specified t_W_min = 10ns at 5V — directly matching 2 × t_pd.
Practical SR Latch ICs
74HC279 — Quad SR NAND Latch
The 74HC279 contains four SR latches implemented with NAND gates:
- Two latches have single S̄ and R̄ inputs (2-input NAND gates)
- Two latches have two S̄ inputs (S̄1, S̄2) and one R̄ input (3-input NAND for Set, 2-input NAND for Reset) The dual Set inputs allow asserting Set via either S̄1=0 OR S̄2=0 (OR logic for Set with NAND)
Pin assignments (16-pin DIP):
- Latch 1: R̄1(1), S̄1(2) → Q1(3)
- Latch 2: R̄2(4), S̄2_1(5), S̄2_2(6) → Q2(7) (two Set inputs)
- Latch 3: R̄3(10), S̄3_1(11), S̄3_2(12) → Q3(13) (two Set inputs)
- Latch 4: R̄4(14), S̄4(15) → Q4(16)…
Actually the 74HC279 pinout with Q̄ outputs not always present. Let me note: the 74HC279 provides Q outputs only (no Q̄). For applications needing Q̄, use NAND gates to form the latch directly from 74HC00 gates.
Supply: 2V–6V, propagation delay ~10ns at 5V, minimum pulse width 10ns.
Building SR Latches from Standard ICs
Since SR latches are naturally formed by cross-coupling any inverting gate, you can build them from gates you already have in a design:
NAND SR latch from 74HC00 (two gates of four):
- Gate 1 (74HC00 pins 1,2→3): S̄ to pin 1, feedback Q̄ to pin 2, output Q at pin 3
- Gate 2 (74HC00 pins 4,5→6): R̄ to pin 4, feedback Q to pin 5, output Q̄ at pin 6
- Connect pin 3 to pin 5 (Q feeds back to Gate 2)
- Connect pin 6 to pin 2 (Q̄ feeds back to Gate 1)
Two gates from a single quad NAND IC, two spare gates for other logic. This is often the most economical approach.
NOR SR latch from 74HC02 (two gates of four):
- Gate 1 (74HC02 pins 1,2,3 — output first for NOR!): output Q at pin 1, S to pin 2, Q̄ feedback to pin 3
- Gate 2: output Q̄ at pin 4, R to pin 5, Q feedback to pin 6
- Connect pin 1 to pin 6, connect pin 4 to pin 3
Important: 74HC02 pin ordering is output-first (Y, A, B), unlike 74HC00 which is input-first (A, B, Y). Always verify the datasheet before wiring.
Application 1: Switch Debounce — The Classic NAND SR Application
Why Mechanical Switches Bounce
When a mechanical switch closes, the metal contacts do not make clean, single contact. The spring mechanism causes the contacts to bounce — making and breaking contact multiple times in rapid succession before settling to a stable closed position. This bouncing period lasts typically 1–50ms depending on the switch type and quality.
Consequences of switch bounce:
A microcontroller reading a switch input at 10MHz samples it 10,000 times per millisecond. In 10ms of bounce, the switch may appear to toggle hundreds of times. Code that counts switch presses may count 50 presses from a single physical press. Code that waits for a falling edge may trigger on every bounce. Latched outputs may toggle wildly.
The NAND SR Latch Debounce Circuit
Circuit for an SPDT (single-pole double-throw) switch:
VCC ──[10kΩ]──┬──── S̄ ──┐
│ NAND SR ──── Q (clean output)
│ Latch
VCC ──[10kΩ]──┴──── R̄ ──┘
Switch center terminal connects to GND.
In position 1 (toward S̄): S̄ pulled to GND through switch → S̄=0 (Set active)
In position 2 (toward R̄): R̄ pulled to GND through switch → R̄=0 (Reset active)
When switch moves: one line goes HIGH (pull-up to VCC), other goes LOW (switch to GND)Why bounce is irrelevant:
When the switch first makes contact with the S̄ terminal (moving from R̄ position):
- S̄ goes LOW (contact made) → NAND SR latch sets Q=1
- Switch bounces: S̄ goes HIGH momentarily → latch enters hold state, Q remains 1
- Switch bounces: S̄ goes LOW again → latch tries to set again, Q already 1, no change
- Switch settles: S̄ stays LOW → Q=1 stably
The latch responds to the FIRST contact (immediate transition) and ignores all subsequent bounces. The output Q is clean — it transitions exactly once from 0 to 1 (or 1 to 0) for each physical switch throw.
Timing advantage over RC debounce: The SR latch debounce is instantaneous — Q transitions immediately on first contact, without any delay. RC + Schmitt trigger debounce deliberately slows the signal to outlast the bounce period (adding 5–50ms of latency). The SR latch method gives immediate, clean transitions with zero added delay.
Limitation: Requires an SPDT switch. For SPST (single-pole single-throw) switches with only one terminal and one position, the RC + Schmitt approach or software debounce must be used — the latch needs two complementary inputs to implement the hold state.
Complete Debounce Circuit with LED Output
Components:
- 1× 74HC00 (Quad NAND) — uses 2 gates for SR latch, 2 gates spare
- 1× SPDT switch (center terminal to GND)
- 2× 10kΩ pull-up resistors (one per switch terminal)
- 1× LED + 470Ω resistor
- 100nF decoupling capacitor
Connections:
5V ──[10kΩ]──┬── pin 1 (1A of NAND1, acts as S̄)
│
Switch ────── center terminal
│
5V ──[10kΩ]──┴── pin 4 (2A of NAND2, acts as R̄)
NAND1: pins 1,2 → Q (pin 3). Pin 2 receives Q̄ feedback from pin 6.
NAND2: pins 4,5 → Q̄ (pin 6). Pin 5 receives Q feedback from pin 3.
Q (pin 3) → 470Ω → LED → GNDBehavior test:
- Switch to position 1 (S̄ side): LED turns on immediately and cleanly
- Switch to position 2 (R̄ side): LED turns off immediately and cleanly
- No flicker, no multiple toggles, no bounce artifacts
Application 2: SR Latch in a Burglar Alarm
Alarm Latching Behavior
An important property of SR latches in alarm systems: unlike a simple gate circuit that goes HIGH when triggered and immediately goes LOW when the trigger clears, a latched alarm stays triggered (Q=1) even after the triggering condition is removed. The alarm can only be reset by a deliberate reset action (pressing a reset button), not by the burglar simply closing the window they opened.
Logic requirement:
- Any sensor activation → Set the latch (alarm sounds)
- Alarm continues even after sensor clears
- RESET button → Reset the latch (alarm silences)
Circuit Design
Multiple sensors (window, door, motion) using NOR SR latch:
Since NOR SR latch Set input is active-HIGH, any sensor pulling S HIGH will set the alarm:
Sensor outputs (any normally-LOW, goes HIGH on trigger):
- Door sensor → OR gate input
- Window sensor → OR gate input
- Motion sensor → OR gate input
OR gate output → S input of NOR SR latchWait — the NOR SR latch needs separate Set and Reset paths. For multiple sensors ORed together:
S = Door_trigger OR Window_trigger OR Motion_trigger
R = Reset_button_pressGate implementation:
- 74HC32 (OR): combines all sensor signals → S
- 74HC02 (NOR): two gates cross-coupled as SR latch, S and R inputs
- Alarm output: Q drives transistor → siren
Complete circuit:
Door_sensor ──┐
Window_sensor─┤──[74HC32 OR gate]──→ S ──┐
Motion_sensor ┘ NOR SR Latch → Q → Siren driver
R ──┘
RESET_button (momentary press → HIGH) ──→ RPower-on initialization: When power is first applied, the latch state is unpredictable. Add a power-on reset circuit: a 10µF capacitor + 100kΩ resistor from VCC to the R input creates a brief HIGH pulse on R at power-up, initializing Q=0 (alarm off) before the system becomes operational.
Alarm silencing with key reset: Replace RESET button with a key switch. The alarm can only be reset by authorized personnel with the key, even while sensors are still triggered.
Test scenario:
- Power up: R briefly HIGH → Q=0, alarm off ✓
- Window opens: Window_sensor goes HIGH → S=HIGH → Q=1, alarm sounds ✓
- Burglar quickly closes window: Window_sensor goes LOW → S=LOW → latch holds Q=1, alarm continues ✓
- Authorized reset: RESET pressed → R=HIGH → Q=0, alarm silences ✓
- Sensors still clear: S=LOW, R=LOW → latch holds Q=0 ✓
Application 3: SR Latch as a Data Valid Indicator
Handshake Protocol
In digital communication systems, a transmitter sends data and must indicate when the data is valid (settled and ready to read). A receiver reads the data and must indicate when it has finished reading. The SR latch implements a simple handshake:
Protocol:
- Transmitter places data on bus
- Transmitter asserts DATA_VALID (sets the SR latch: Q=1)
- Receiver detects Q=1, reads data
- Receiver asserts DATA_READ (resets the SR latch: Q=0)
- Transmitter detects Q=0, places next data on bus
The SR latch serves as a flag that persists until explicitly cleared — the transmitter sets it, the receiver clears it. Neither side needs to continuously hold its signal; the latch stores the handshake state between events.
Implementation:
- S = DATA_VALID (one-shot pulse from transmitter)
- R = DATA_READ (one-shot pulse from receiver)
- Q = VALID_FLAG (status available to both sides)
The Q̄ output also provides a BUFFER_FREE signal to the transmitter (Q̄=1 when receiver has cleared the latch and new data can be sent).
Application 4: SR Latch in a Motor Direction Controller
Mechanical Interlock
A motor controller for a reversible motor must prevent simultaneous activation of FORWARD and REVERSE outputs — this would short-circuit the H-bridge (as described in Article 74). Two pushbuttons (FORWARD and REVERSE) must be interlocked: pressing one should not activate if the other is already active.
Using NAND SR latch for interlocked control:
FORWARD_btn (active-LOW, SPST → GND when pressed) → S̄ input
REVERSE_btn (active-LOW, SPST → GND when pressed) → R̄ input
Q = FORWARD signal (HIGH = motor runs forward)
Q̄ = REVERSE signal (HIGH = motor runs reverse)Behavior:
- Press FORWARD: S̄ goes LOW → Q=1 (forward), Q̄=0 (reverse off)
- While forward running, press REVERSE: R̄ goes LOW → Q=0 (forward off), Q̄=1 (reverse on)
- Release both buttons: latch holds current direction in hold state
- STOP button: separate reset circuit forces Q=Q̄=0 through additional NOR gate…
Actually both Q=0 and Q̄=0 would require both buttons pressed simultaneously (forbidden state). A cleaner implementation:
STOP function: Add a STOP button that connects a 3-input NAND (one input from Q, one from Q̄ feedback path, one from STOP̄) — or more practically, use the STOP button to assert both R̄ and S̄ simultaneously at lower priority through additional logic.
A simpler stop: use the NAND SR latch for SET/RESET only, and gate the Q and Q̄ outputs with a separate ENABLE signal (AND gates): FORWARD = Q AND ENABLE, REVERSE = Q̄ AND ENABLE. The STOP button deasserts ENABLE. This cleanly separates the direction memory (SR latch) from the run/stop control (ENABLE).
The SR Latch as the Foundation of All Flip-Flops
Building a D Latch from an SR Latch
Add logic to derive S and R from a single D input with enable EN:
S_internal = D AND EN
R_internal = D̄ AND EN (= NOT D AND EN)Gate implementation: two AND gates (one for S, one for R), one NOT gate (for D̄). Feed S_internal and R_internal to the NOR SR latch. The NOT gate guarantees S and R are never simultaneously HIGH (since D and D̄ are complementary).
The result is the gated D latch: transparent when EN=1 (Q follows D), latched when EN=0 (Q holds).
Using NAND implementation directly: Replace the NOR SR latch + AND gates with a 4-NAND gated D latch:
NAND1: inputs D, EN → S̄_internal = NAND(D, EN)
NAND2: inputs D̄, EN → R̄_internal = NAND(D̄, EN) [where D̄ from NOT gate or 3rd NAND with D,D]
NAND SR latch: NAND3 and NAND4 cross-coupledThis is the standard 4-gate (plus NOT) D latch — the internal structure of every D latch in every synchronous IC.
Building Edge-Triggered D Flip-Flop from Two SR Latches
Master-slave configuration (positive-edge-triggered):
Master SR latch: S_master = D AND CLK̄, R_master = D̄ AND CLK̄
- Active (transparent) when CLK=0
- Samples D during CLK low phase
Slave SR latch: S_slave = Q_master AND CLK, R_slave = Q̄_master AND CLK
- Active (transparent) when CLK=1
- Transfers master’s captured value to Q during CLK high phase
Q transitions at the rising edge (CLK 0→1): that is when the master’s value (captured during CLK=0) transfers to the slave (now enabled by CLK=1).
The 74HC74 D flip-flop implements exactly this structure internally, with additional logic for the PRE̅ and CLR̅ asynchronous inputs.
The SR Latch Hierarchy
Cross-coupled inverters (unstable bistable — no control)
↓
NOR / NAND SR latch (bistable with Set/Reset control)
↓
Gated SR latch (adds clock enable)
↓
Gated D latch (single input, no forbidden state)
↓
Master-slave D flip-flop (edge triggering via two latches)
↓
JK flip-flop (adds toggle: SR latch + feedback gating)
↓
T flip-flop (JK with J=K — pure toggle)Every step adds one constraint or capability to the SR latch. Understanding each transition makes the hierarchy clear rather than arbitrary.
Timing Analysis: SR Latch Propagation
Propagation Delay Through the SR Latch
When S is asserted (NOR latch, S=0→1):
Path 1 — Direct: Gate 1 sees S=1 → output Q̄ falls (Gate 1 propagation delay t_pd1) Path 2 — Feedback: Gate 2 sees new Q̄ → output Q rises (Gate 2 propagation delay t_pd2)
Total time for latch to fully settle into new stable state:
t_settle = t_pd1 + t_pd2 = 2 × t_pdFor 74HC gates (t_pd ≈ 7ns at 5V):
t_settle ≈ 14nsThis is the minimum time after asserting S before the latch output Q is guaranteed valid. For the 74HC279: specified propagation delay = 13ns at 5V, consistent with 2 × t_pd.
Propagation Delay Asymmetry
In real CMOS implementations, the SET and RESET operations may have slightly different propagation delays due to:
- PMOS vs. NMOS driving the output node (PMOS is inherently slower)
- Load capacitance differences on Q vs. Q̄
The 74HC279 datasheet specifies:
- t_pd from S̄ to Q: 13ns typical, 20ns max at 5V
- t_pd from R̄ to Q̄: 13ns typical, 20ns max at 5V
Symmetric for this device, but always check the specific datasheet for timing-critical applications.
Minimum Input Pulse Width
From the settling analysis, S (or R) must be held active for at least 2 × t_pd to guarantee the latch fully settles:
t_W(S) or t_W(R) ≥ 2 × t_pd ≈ 14nsFor the 74HC279: specified minimum pulse width = 10ns at 5V. This is slightly less than 2 × t_pd because the device’s internal structure completes the feedback faster than worst-case external gate delays.
Recovery Time: Consecutive Operations
After resetting (R active), how quickly can Set be asserted? The latch must fully settle in the reset state before set can reliably operate:
t_recovery ≥ t_pd (at least one gate delay for latch to stabilize after reset)For very fast consecutive set/reset operations, this recovery time must be respected. In practice, SR latches used in debounce and alarm applications have event rates far below the timing limits.
Common Mistakes and How to Avoid Them
Mistake 1: Asserting both Set and Reset simultaneously
Intentionally or through a circuit bug, asserting both S and R (NOR) or S̄ and R̄ (NAND) simultaneously forces both outputs to the same state and causes undefined behavior when inputs are released. Analyze your control logic to prove this can never occur — add hardware interlocks (AND/OR gates at the inputs) if necessary.
Mistake 2: Using a single NOR gate’s input without verifying which is S and which is R
The NOR SR latch’s output assignment depends critically on which control input connects to which gate. As traced above, S connects to the gate whose output is Q̄ (not Q). Connecting S to the gate whose output is Q gives an SR-bar latch with inverted behavior — setting when R is active and resetting when S is active. Always draw and label the full circuit before wiring.
Mistake 3: Forgetting that NAND SR latch inputs are active-LOW
A NAND SR latch with R̄=0 (LOW) RESETS the latch. Many designers, accustomed to active-HIGH NOR SR latches, accidentally connect active-HIGH control signals to a NAND latch and get inverted behavior. Label inputs as S̄ and R̄ explicitly to remind yourself of the active-LOW convention.
Mistake 4: Not initializing the latch at power-up
At power-up, the latch state is indeterminate — it could be in either stable state depending on transistor process variations and power-supply ramp characteristics. For alarm systems, motor controllers, and any application where the power-up state matters, add a power-on reset circuit (RC + resistor creating a brief pulse on R̄ or R) to initialize Q to a known state.
Mistake 5: Using SPST switch with SR latch debounce
The SR latch debounce requires an SPDT switch — it needs two complementary switching signals. An SPST switch only provides one signal; when it opens, neither S nor R is asserted and the latch simply holds. This works IF the switch is clean when opening (most switches bounce on both make and break). For SPST debouncing, use RC + Schmitt trigger instead.
Mistake 6: Applying S or R pulse too briefly
Input pulses shorter than t_W_min (≈14ns for 74HC) may not fully establish the new state. In microcontroller-driven SR latches, this is usually not a concern (even a 1µs write pulse is 70× longer than t_W_min). In very high-speed circuits, verify that the pulse generator meets the minimum pulse width requirement.
Summary
The SR latch is the fundamental digital memory circuit — two cross-coupled NOR or NAND gates with Set and Reset inputs that provide bistability with control. The NOR version uses active-HIGH inputs (S=1 sets, R=1 resets, S=R=0 holds, S=R=1 forbidden). The NAND version uses active-LOW inputs (S̄=0 sets, R̄=0 resets, S̄=R̄=1 holds, S̄=R̄=0 forbidden).
The hold state works because the cross-coupled gates form self-reinforcing feedback — each gate’s output feeds back to maintain its complement’s current state. The set and reset operations work because asserting a control input overrides the feedback, forcing one gate’s output to a defined value and allowing the other to follow. The forbidden state forces both outputs to the same value, creating an internally inconsistent condition that resolves unpredictably when control inputs are released.
Timing analysis shows that the latch requires approximately 2 × t_pd to fully settle after a Set or Reset operation — about 14ns for 74HC gates. The NAND SR latch is more practically useful due to wider availability, faster CMOS implementation, and natural compatibility with active-LOW switch signals.
The four applications — switch debounce, burglar alarm, data valid handshake, and motor direction interlock — demonstrate how the SR latch’s latching behavior (holding state without continuous input) is exactly what these applications require. The structural analysis shows how the SR latch is the foundation from which every more complex flip-flop type is derived by adding successive layers of control logic.
