NAND and NOR gates are called universal gates because any logic function — AND, OR, NOT, XOR, or any combination — can be implemented using only NAND gates or only NOR gates, without needing any other gate type. This universality, combined with the fact that CMOS transistor technology naturally produces NAND and NOR functions more efficiently than AND or OR, makes them the dominant gates in all modern digital integrated circuits. Understanding how to convert any logic design to all-NAND or all-NOR implementation is a fundamental skill for digital circuit design.
Introduction: Why NAND and NOR Rule Digital Electronics
If you asked a digital logic textbook which gates are most fundamental, it would probably say AND, OR, and NOT — the three operations of Boolean algebra. Ask a chip designer the same question, and the answer is almost certainly NAND and NOR. The gap between these answers reveals something important about the difference between mathematical elegance and engineering reality.
CMOS (Complementary Metal-Oxide-Semiconductor) transistor technology — the technology in every digital device from a microcontroller to a superprocessor — naturally implements NAND and NOR functions in a single gate stage. An AND gate in CMOS requires a NAND gate followed by an inverter — two stages, more transistors, more area, more power. Similarly, an OR gate requires a NOR gate and an inverter. From a silicon perspective, NAND and NOR are the primitive operations; AND and OR are derived. This is the exact reverse of how Boolean algebra is typically taught.
Beyond implementation efficiency, NAND and NOR gates possess a remarkable mathematical property: universality. Starting from either NAND alone or NOR alone, you can construct any AND, OR, or NOT gate — and therefore any combinational logic function whatsoever. A digital circuit library with a single gate type (NAND or NOR) is complete. In the early days of TTL integrated circuits, this meant a designer needed to stock only one component type — the 7400 quad NAND — to build any logic circuit. The same principle applies today in FPGA lookup tables and standard cell ASIC libraries.
This article provides a thorough treatment of NAND and NOR gates: their truth tables and Boolean expressions, their CMOS transistor-level implementations, the proofs of their universality with complete conversion recipes, how to convert any AND/OR/NOT design to an all-NAND or all-NOR implementation, the practical ICs available in standard logic families, and five complete design examples demonstrating the power of working entirely in NAND or NOR logic.
The NAND Gate: NOT-AND
Truth Table and Boolean Expression
The NAND gate combines AND followed by NOT — its output is the complement of an AND gate:
Two-input NAND truth table:
| A | B | A·B | Q = ̄(A·B) |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
Output is LOW only when ALL inputs are HIGH. Output is HIGH for every other combination — three out of four rows for a 2-input gate.
Boolean expression:
Q = ̄(A·B) (NAND notation)
Q = A ↑ B (Sheffer stroke notation — less common)Key characteristic: NAND output defaults HIGH. It takes all inputs being HIGH simultaneously to pull the output LOW. This “active-LOW output when all inputs HIGH” behavior is fundamental to understanding NAND logic.
NAND Gate Schematic Symbol
The NAND symbol is an AND gate body (flat input side, curved D-shaped output) with a bubble (inversion circle) at the output:
____
A --| \
| )o-- Q
B --|____/
The bubble indicates inversion. Any gate symbol with a bubble at the output produces the complement of what that body shape normally implies.
CMOS Implementation of NAND
A CMOS NAND gate uses four transistors — two PMOS (pull-up) in parallel and two NMOS (pull-down) in series:
VCC ─┬──────┬─
│ │
[P1] [P2] ← PMOS pull-up network (parallel)
│ │
└──┬───┘
│
OUT
│
[N1] ← NMOS pull-down network (series)
│
[N2]
│
GND
When A=0 OR B=0: At least one PMOS transistor conducts (PMOS turns on when gate is LOW), pulling OUT toward VCC. At least one NMOS is off (NMOS turns off when gate is LOW), breaking the pull-down path. OUT = HIGH. ✓
When A=1 AND B=1: Both PMOS transistors are off (PMOS turns off when gate is HIGH), disconnecting VCC. Both NMOS transistors conduct (NMOS turns on when gate is HIGH), creating a path from OUT to GND through both series N1 and N2. OUT = LOW. ✓
Why CMOS NAND uses parallel PMOS and series NMOS:
- Pull-up network (PMOS) is the complement of the pull-down network (NMOS)
- For NAND: output HIGH when any input LOW → PMOS in parallel (either one suffices)
- For NAND: output LOW when ALL inputs HIGH → NMOS in series (both required)
- This complementary structure guarantees the output is never simultaneously connected to both VCC and GND (no shoot-through in steady state)
Transistor count: A 2-input NAND gate uses 4 transistors. An AND gate requires a NAND plus an inverter — 4 + 2 = 6 transistors. NAND is inherently more efficient.
NMOS series resistance disadvantage: When N NMOS transistors are stacked in series (for an N-input NAND), the total pull-down resistance scales with N. For 4-input NAND, four NMOS in series have 4× the resistance of one NMOS — slowing the discharge and reducing drive strength. This is why practical CMOS libraries limit NAND gates to 4 inputs maximum (2-, 3-, and 4-input are standard; 5+ input NAND is unusual).
The NOR Gate: NOT-OR
Truth Table and Boolean Expression
The NOR gate combines OR followed by NOT — its output is the complement of an OR gate:
Two-input NOR truth table:
| A | B | A+B | Q = ̄(A+B) |
|---|---|---|---|
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 |
Output is HIGH only when ALL inputs are LOW. Output is LOW for every other combination — three out of four rows for a 2-input gate.
Boolean expression:
Q = ̄(A+B) (NOR notation)
Q = A ↓ B (Peirce arrow notation — less common)Key characteristic: NOR output defaults LOW. It takes ALL inputs being LOW simultaneously to produce a HIGH output. This “active-HIGH output only when all inputs LOW” behavior is fundamental to NOR logic.
NOR Gate Schematic Symbol
The NOR symbol is an OR gate body (curved input side, pointed output) with a bubble at the output:
___
A --\ \
) >o-- Q
B --/___/CMOS Implementation of NOR
A CMOS NOR gate uses four transistors — two PMOS (pull-up) in series and two NMOS (pull-down) in parallel:
VCC ─
│
[P1] ← PMOS pull-up network (series)
│
[P2]
│
OUT
┌┴┐
[N1][N2] ← NMOS pull-down network (parallel)
└┬┘
GNDWhen A=0 AND B=0: Both PMOS conduct (series path intact), OUT connects to VCC. Both NMOS off, OUT disconnected from GND. OUT = HIGH. ✓
When A=1 OR B=1: At least one PMOS is off, breaking the series pull-up path. At least one NMOS conducts, connecting OUT to GND. OUT = LOW. ✓
PMOS series resistance disadvantage: PMOS transistors in series (for NOR) suffer the same resistance stacking problem as NMOS in series (for NAND). PMOS transistors already have about 2–3× higher resistance than NMOS of the same size (due to lower hole mobility). Stacking them in series for NOR makes the pull-up path even weaker than the NAND pull-down path. This is why NOR gates are generally slower than NAND gates in CMOS — NAND is preferred in most digital design.
Consequence: In most CMOS standard cell libraries, NAND gates are more commonly used than NOR gates due to their superior speed and drive strength.
NAND Universality: Building Everything from NAND
Proof by Construction
To prove NAND is universal, we need to show that AND, OR, and NOT can all be implemented using only NAND gates. Since AND, OR, NOT form a complete set (any logic function can be built from them), anything that can implement AND, OR, and NOT can implement anything.
NOT from NAND
Connect both inputs of a NAND gate together (tie A and B to the same signal):
Q = ̄(A·A) = ̄ABecause A·A = A (idempotent law), NAND with both inputs tied gives NOT.
Circuit: Connect both input pins to the input signal. Output is the inverted signal.
Verification:
- Input A=0: Q = ̄(0·0) = ̄0 = 1 ✓
- Input A=1: Q = ̄(1·1) = ̄1 = 0 ✓
AND from NAND
AND = NAND followed by NOT. Since NOT = NAND with tied inputs:
A·B = ̄(̄(A·B))Two NAND gates in series: the first computes NAND(A,B), the second inverts it (with tied inputs).
Circuit:
- NAND gate 1: inputs A and B → output = ̄(A·B)
- NAND gate 2 (as NOT): both inputs connected to gate 1 output → output = ̄(̄(A·B)) = A·B
Gate count: 2 NAND gates to implement 1 AND gate.
OR from NAND
Using De Morgan’s law: A+B = ̄(Ā·B̄)
So: A+B = NAND(Ā, B̄) = NAND(NOT A, NOT B)
Since NOT = NAND with tied inputs:
A+B = NAND(NAND(A,A), NAND(B,B))Three NAND gates: two inverters on the inputs, one NAND on the inverted inputs.
Circuit:
- NAND gate 1 (NOT A): both inputs = A → output = Ā
- NAND gate 2 (NOT B): both inputs = B → output = B̄
- NAND gate 3: inputs Ā and B̄ → output = ̄(Ā·B̄) = A+B
Gate count: 3 NAND gates to implement 1 OR gate.
Complete Conversion Table: NAND Implementations
| Function | NAND Implementation | Gate Count |
|---|---|---|
| NOT A | NAND(A, A) | 1 NAND |
| A AND B | NAND(NAND(A,B), NAND(A,B)) | 2 NAND |
| A OR B | NAND(NAND(A,A), NAND(B,B)) | 3 NAND |
| A NAND B | NAND(A, B) | 1 NAND |
| A NOR B | NAND(NAND(NAND(A,A),NAND(B,B)), NAND(NAND(A,A),NAND(B,B))) | 5 NAND |
| A XOR B | NAND(NAND(A,NAND(A,B)), NAND(B,NAND(A,B))) | 4 NAND |
The XOR from 4 NAND gates is particularly elegant and important — memorize this one.
XOR from 4 NAND Gates: Derivation
XOR: Q = A⊕B = Ā·B + A·B̄
The 4-NAND implementation:
N1 = NAND(A, B) → N1 = ̄(A·B)
N2 = NAND(A, N1) → N2 = ̄(A·N1) = ̄(A·̄(A·B))
N3 = NAND(B, N1) → N3 = ̄(B·N1) = ̄(B·̄(A·B))
Q = NAND(N2, N3) → Q = ̄(N2·N3)Proof:
N2 = ̄(A·̄(A·B))
= ̄A + A·B (De Morgan's: ̄(A·X) = Ā + X̄, here X = ̄(A·B), X̄ = A·B)
= Ā + A·B
= Ā + B (absorption: Ā + A·B = Ā + B)
N3 = ̄(B·̄(A·B)) = B̄ + A (by symmetry)
Q = ̄(N2·N3) = ̄((Ā+B)·(A+B̄))Expanding: (Ā+B)·(A+B̄) = Ā·A + Ā·B̄ + B·A + B·B̄ = 0 + Ā·B̄ + A·B + 0 = Ā·B̄ + A·B = XNOR
Q = ̄(XNOR) = XOR ✓
This is the standard 4-NAND XOR — one of the most efficient XOR implementations in CMOS.
NOR Universality: Building Everything from NOR
NOT from NOR
Connect both inputs together:
Q = ̄(A+A) = ̄ABecause A+A = A (idempotent law), NOR with tied inputs gives NOT.
OR from NOR
OR = NOR followed by NOT:
A+B = ̄(̄(A+B))Two NOR gates in series: first computes NOR(A,B), second inverts it.
AND from NOR
Using De Morgan’s law: A·B = ̄(Ā+B̄)
So: A·B = NOR(Ā, B̄) = NOR(NOT A, NOT B)
Three NOR gates: two inverters on inputs, one NOR on inverted inputs.
A·B = NOR(NOR(A,A), NOR(B,B))Complete Conversion Table: NOR Implementations
| Function | NOR Implementation | Gate Count |
|---|---|---|
| NOT A | NOR(A, A) | 1 NOR |
| A OR B | NOR(NOR(A,B), NOR(A,B)) | 2 NOR |
| A AND B | NOR(NOR(A,A), NOR(B,B)) | 3 NOR |
| A NOR B | NOR(A, B) | 1 NOR |
| A NAND B | NOR(NOR(NOR(A,A),NOR(B,B)), NOR(NOR(A,A),NOR(B,B))) | 5 NOR |
| A XOR B | NOR(NOR(A,NOR(A,B)), NOR(B,NOR(A,B))) | 4 NOR |
Note the exact symmetry between NAND and NOR conversion tables — AND/OR swap, NAND/NOR swap, but the structure and gate counts are identical.
NAND vs. NOR: Which to Use?
| Factor | NAND Preferred | NOR Preferred |
|---|---|---|
| CMOS speed | ✓ (NMOS series, faster) | ✗ (PMOS series, slower) |
| Standard cell density | ✓ (smaller area) | ✗ |
| Sum-of-Products expression | ✓ (direct implementation) | ✗ |
| Product-of-Sums expression | ✗ | ✓ (direct implementation) |
| Active-LOW logic | ✓ (NAND output active-LOW) | ✗ |
| Active-HIGH reset logic | ✗ | ✓ (NOR output active-HIGH when all inputs LOW) |
| SR latch | Both work equally | Both work equally |
General rule: Prefer NAND gates for most digital logic design. NOR gates excel in specific situations: Product-of-Sums implementations, active-LOW input logic, and SR latches (where both produce equivalent results).
Converting AND/OR/NOT Designs to All-NAND
Given any logic circuit in AND/OR/NOT form, a systematic procedure converts it to all-NAND:
Method 1: Direct Substitution
Replace each gate type with its NAND equivalent using the conversion table:
- Each NOT → 1 NAND (tied inputs)
- Each AND → 2 NAND (NAND + NAND-as-NOT)
- Each OR → 3 NAND (two NAND-NOT inputs + one NAND)
Problem: This approach is correct but not minimal — it doesn’t take advantage of cancellations that occur when NAND inversions meet at gate boundaries.
Method 2: Bubble Pushing (DeMorgan’s Law Graphically)
The elegant method used by professional designers exploits the fact that a bubble on an AND gate output is equivalent to a bubble on both OR gate inputs (De Morgan’s law), and vice versa.
Rules:
- Replace all AND gates with NAND gates (add bubble at output)
- Replace all OR gates with NAND gates (add bubbles at inputs — because ̄Ā·̄B̄ = NAND(Ā,B̄) = OR(A,B) by De Morgan)
- Where two bubbles meet (output bubble of one gate → input bubble of the next), cancel them (double inversion = no inversion)
- Any remaining unpaired bubbles need inverters (tied-input NAND)
Result: Paired bubbles cancel; unpaired bubbles require inverters. The final circuit often has far fewer inverters than Method 1 suggests.
Method 2 Example: Convert Q = A·B + C·D to all-NAND
Original AND/OR/NOT circuit:
- Gate 1 (AND): A, B → A·B
- Gate 2 (AND): C, D → C·D
- Gate 3 (OR): A·B, C·D → Q
Step 1: Replace AND gates with NAND gates (bubbles on outputs):
- Gate 1 (NAND): A, B → ̄(A·B) [has output bubble]
- Gate 2 (NAND): C, D → ̄(C·D) [has output bubble]
- Gate 3 (still OR): ̄(A·B), ̄(C·D) → Q
Step 2: Replace OR gate with a NAND that has input bubbles (De Morgan equivalent): A NAND gate with input bubbles is equivalent to: invert inputs, then NAND = ̄(Ā·B̄) = A+B (OR) So: Gate 3 (NAND with input bubbles): inputs ̄(A·B) and ̄(C·D)
Step 3: Cancel paired bubbles:
- Gate 1 output bubble meets Gate 3 left input bubble → cancel (double inversion)
- Gate 2 output bubble meets Gate 3 right input bubble → cancel
Result:
- Gate 1 (NAND): A, B → output goes directly to Gate 3 left input
- Gate 2 (NAND): C, D → output goes directly to Gate 3 right input
- Gate 3 (NAND): Gate1_out, Gate2_out → Q
Q = ̄(̄(A·B) · ̄(C·D)) = A·B + C·D (by De Morgan)Three NAND gates, zero inverters — exactly the same count as three AND/OR gates. The bubble cancellation eliminated what would have been two inverters in the direct substitution approach. This is the two-level NAND-NAND circuit — the standard implementation of Sum-of-Products expressions.
The NAND-NAND Pattern for Sum of Products
Any Sum of Products expression (Q = A·B + C·D + E·F…) implements directly as a two-level NAND-NAND circuit:
Level 1: One NAND gate per product term (each AND term becomes a NAND) Level 2: One NAND gate combining all level-1 outputs
The level-2 NAND acts as an OR gate (via De Morgan) because: ̄(̄P1 · ̄P2 · ̄P3) = P1 + P2 + P3
This direct SoP → NAND-NAND mapping is why Sum of Products is the preferred form for NAND-based implementations. The Karnaugh map minimizes the number of product terms and literals, which directly minimizes the number of NAND gates and their input counts.
The NOR-NOR Pattern for Product of Sums
Symmetrically, any Product of Sums expression implements as a two-level NOR-NOR circuit:
Level 1: One NOR gate per sum term Level 2: One NOR gate combining all level-1 outputs
This is why Product of Sums is the preferred form for NOR-based implementations.
Practical NAND and NOR Gate ICs
NAND Gate ICs (74HC Family)
| IC | Description | Gates | Inputs | Package |
|---|---|---|---|---|
| 74HC00 | Quad 2-input NAND | 4 | 2 | 14-DIP/SOIC |
| 74HC10 | Triple 3-input NAND | 3 | 3 | 14-DIP/SOIC |
| 74HC20 | Dual 4-input NAND | 2 | 4 | 14-DIP/SOIC |
| 74HC30 | Single 8-input NAND | 1 | 8 | 14-DIP/SOIC |
| 74HC132 | Quad 2-input NAND (Schmitt) | 4 | 2 | 14-DIP/SOIC |
74HC00 pin assignment (the most important IC to know):
- Pins 1,2 → 3 (1A, 1B → 1Y)
- Pins 4,5 → 6 (2A, 2B → 2Y)
- Pins 9,10 → 8 (3A, 3B → 3Y)
- Pins 12,13 → 11 (4A, 4B → 4Y)
- Pin 7: GND, Pin 14: VCC
74HC132 (Schmitt trigger inputs): Same pinout and function as 74HC00 but with Schmitt trigger inputs — adds hysteresis for noise-immune switching. Essential for slow or noisy input signals. Used extensively in switch debouncing, oscillators, and signal conditioning.
NOR Gate ICs (74HC Family)
| IC | Description | Gates | Inputs | Package |
|---|---|---|---|---|
| 74HC02 | Quad 2-input NOR | 4 | 2 | 14-DIP/SOIC |
| 74HC27 | Triple 3-input NOR | 3 | 3 | 14-DIP/SOIC |
| 74HC4002 | Dual 4-input NOR | 2 | 4 | 14-DIP/SOIC |
74HC02 pin assignment:
- Pins 1,2 → 3 (1A, 1B → 1Y) — Note: output pin is FIRST for NOR vs. last for NAND
- Wait — 74HC02 uses output-first pinout: pin 1 is 1Y, pins 2,3 are 1A,1B
- Pins 4,5,6 (2Y, 2A, 2B); Pins 8,9,10 (3Y, 3A, 3B); Pins 11,12,13 (4Y, 4A, 4B)
- Pin 7: GND, Pin 14: VCC
Critical difference: The 74HC00 (NAND) and 74HC02 (NOR) have DIFFERENT pinouts despite the same package. The NOR gate output comes before its inputs on each group (Y, A, B ordering), while the NAND gate has inputs before output (A, B, Y). Always check the datasheet — do not assume they are interchangeable.
The Historic 7400: Why It Matters
The 7400 quad 2-input NAND (TTL version of 74HC00) is arguably the most historically important logic IC ever made. Introduced by Texas Instruments in 1964, it defined the 7400 series logic family that dominated electronics for three decades. Virtually every digital system from 1965 through 1990 — computers, calculators, instruments, communications equipment — was built from 7400-series ICs centered around the 7400 NAND gate. The 74HC00 is its modern CMOS successor, pin-compatible, used to this day.
NAND and NOR SR Latches: The Simplest Memory Elements
NAND and NOR gates connected with feedback form SR (Set-Reset) latches — the simplest possible memory elements. These will be explored in detail in the upcoming article on flip-flops, but they deserve introduction here as they are among the most important NAND/NOR applications.
NOR SR Latch
Two NOR gates with their outputs cross-fed to each other’s inputs:
S ──┐ ┌── R
NOR1 NOR2
Q ──┘ └── Q̄More precisely:
- NOR gate 1: inputs S and Q̄ → output Q
- NOR gate 2: inputs R and Q → output Q̄
Behavior:
- S=1, R=0: Q forced HIGH (Set)
- S=0, R=1: Q forced LOW (Reset)
- S=0, R=0: Q retains previous state (Memory)
- S=1, R=1: Forbidden (both outputs LOW, undefined on release)
The NOR SR latch stores one bit of information — Q remembers whether it was last Set or Reset. This is the fundamental memory cell underlying flip-flops, registers, and ultimately all RAM.
Why NOR for SR latch: NOR outputs HIGH when both inputs are LOW (idle state). In the stable memory state (S=0, R=0), each NOR gate sees one LOW control input and one feedback input — the feedback holds the latch in its current state.
NAND SR Latch
Two NAND gates cross-connected, with active-LOW inputs (S̄ and R̄):
- NAND gate 1: inputs S̄ and Q̄ → output Q
- NAND gate 2: inputs R̄ and Q → output Q̄
Behavior:
- S̄=0 (LOW), R̄=1 (HIGH): Q forced HIGH (Set — active LOW)
- S̄=1, R̄=0: Q forced LOW (Reset — active LOW)
- S̄=1, R̄=1: Q retains previous state (Memory)
- S̄=0, R̄=0: Forbidden (both outputs HIGH, undefined on release)
The NAND SR latch has active-LOW inputs — S̄=0 sets, R̄=0 resets. This is natural for NAND gates because NAND outputs HIGH by default; a LOW input is the “active” condition that changes behavior.
Switch debounce application: A mechanical switch with two contacts (one to ground) connected to S̄ and R̄ of a NAND SR latch eliminates switch bounce perfectly — the latch changes state on the first contact and ignores all subsequent bounces. This is the canonical hardware switch debounce circuit.
Complete Design Examples
Design Example 1: All-NAND Implementation of a 3-Input Majority Voter
From Article 79, the majority voter expression is:
Q = A·B + A·C + B·CDirect SoP → NAND-NAND conversion:
Level 1 NAND gates (one per product term):
- N1 = NAND(A, B) = ̄(A·B)
- N2 = NAND(A, C) = ̄(A·C)
- N3 = NAND(B, C) = ̄(B·C)
Level 2 NAND gate (OR of product terms):
- Q = NAND(N1, N2, N3) = ̄(̄(A·B) · ̄(A·C) · ̄(B·C)) = A·B + A·C + B·C (by De Morgan) ✓
Final circuit: 3 two-input NAND gates (Level 1) + 1 three-input NAND gate (Level 2) = 4 NAND gates.
ICs: 74HC00 (uses 3 of 4 two-input NANDs) + 74HC10 (uses 1 of 3 three-input NANDs).
Compare to the AND/OR implementation from Article 79: 3 AND gates (74HC08) + 1 three-input OR (74HC4075) = also 4 gates from 2 ICs. Same gate count, but now all-NAND from two NAND-family ICs. In a design using mostly NAND gates already, this eliminates the need to stock AND and OR ICs separately.
Verification: A=1, B=1, C=0:
- N1 = NAND(1,1) = 0
- N2 = NAND(1,0) = 1
- N3 = NAND(1,0) = 1
- Q = NAND(0,1,1) = 1 ✓ (two inputs active → majority)
A=1, B=0, C=0:
- N1 = NAND(1,0) = 1
- N2 = NAND(1,0) = 1
- N3 = NAND(0,0) = 1
- Q = NAND(1,1,1) = 0 ✓ (only one input → no majority)
Design Example 2: NAND-Based Oscillator (Ring Oscillator)
Application: Generate a square wave clock signal using only NAND gates from a 74HC00.
Method 1: Odd-stage ring oscillator
Three NAND gates connected in a ring, each wired as an inverter (both inputs tied together):
NAND1 (tied inputs) → NAND2 (tied inputs) → NAND3 (tied inputs) → back to NAND1Each gate introduces a propagation delay t_pd ≈ 7ns at 5V for 74HC. With 3 inverters in a ring: oscillation period T = 2 × 3 × t_pd = 42ns → f ≈ 24MHz.
This is too fast for most applications. Add RC delay to slow it down:
Method 2: RC-controlled NAND oscillator
Use one NAND gate as an inverting buffer with RC feedback:
VCC
│
[R1=10kΩ] [R2=1kΩ]
│ │
├──────────────── (INPUT) ─┤
│ │
└──[C=10nF]──(OUTPUT) ─────┘
│
NAND1 (both inputs tied to the feedback node)More precisely, the standard RC NAND oscillator:
- NAND gate 1: both inputs connected to node X → output = X̄
- R (10kΩ): from output back to node X (feedback)
- C (10nF): from node X to GND (sets timing)
- NAND gate 2 (optional buffer): both inputs tied to output of gate 1, provides clean output
Approximate frequency: f ≈ 1 / (2.2 × R × C) = 1 / (2.2 × 10,000 × 10×10⁻⁹) = 1 / (220×10⁻⁶) ≈ 4.5kHz
This simple oscillator is useful for generating audio tones, clock signals for slow logic, and LED blink rates.
Stability note: RC oscillators using NAND gates are NOT precise — frequency varies ±30% with temperature and supply voltage. For precision timing, use a crystal oscillator. The NAND RC oscillator is adequate for non-critical timing: alert tones, visual indicators, slow sequencing.
Component values for common frequencies:
| Frequency | R | C |
|---|---|---|
| 1Hz | 100kΩ | 4.7µF |
| 100Hz | 100kΩ | 47nF |
| 1kHz | 47kΩ | 10nF |
| 10kHz | 10kΩ | 4.7nF |
| 100kHz | 1kΩ | 4.7nF |
For these audible-frequency oscillators, the 74HC132 (Schmitt trigger NAND) gives cleaner output waveforms and more predictable frequency than standard 74HC00.
Design Example 3: All-NAND Alarm System with Acknowledgment
Application: An alarm system with two sensors (DOOR, MOTION), an ARM input, and an ACKNOWLEDGE button. The alarm (ALARM) sounds when the system is armed AND any sensor triggers. Once acknowledged (ACK pressed), the alarm silences until a new trigger occurs.
Logic:
- TRIGGER = DOOR + MOTION (any sensor active)
- ALARM = ARM · TRIGGER · ̄ACK (armed, triggered, not yet acknowledged)
Sum of Products: ALARM = ARM · (DOOR + MOTION) · ̄ACK
Converting to NAND-NAND:
Step 1: Expand to SoP form:
ALARM = ARM·DOOR·ACK̄ + ARM·MOTION·ACK̄Step 2: Map to NAND-NAND:
- N1 = NAND(ARM, DOOR, ACK̄) — needs ACK inverted first
- N2 = NAND(ARM, MOTION, ACK̄) — reuse ACK̄
- N_ACK = NAND(ACK, ACK) → ACK̄ (inverter)
- ALARM = NAND(N1, N2)
Full NAND circuit:
- Gate 1 (NAND as NOT): both inputs = ACK → output = ACK̄
- Gate 2 (NAND, 3-input): inputs ARM, DOOR, ACK̄ → N1
- Gate 3 (NAND, 3-input): inputs ARM, MOTION, ACK̄ → N2
- Gate 4 (NAND, 2-input): inputs N1, N2 → ALARM
Gates needed: one 74HC00 (for gates 1 and 4) + one 74HC10 (for gates 2 and 3).
Buzzer output: ALARM output drives an NPN transistor base through 1kΩ; transistor drives a 5V buzzer. Freewheeling diode across buzzer if it has an inductive coil.
ACK behavior: Pressing ACK pulls ACK̄ LOW, which forces N1 and N2 HIGH (any NAND with a LOW input outputs HIGH), which forces Gate 4 output LOW (ALARM off). This correctly silences the alarm when acknowledged.
Design Example 4: NOR-Based SR Latch for Switch Debounce
Application: A mechanical push button with significant bounce (contacts close and open many times before settling). Clean the output for use with a counter or microcontroller interrupt.
Circuit: Two 74HC02 NOR gates cross-connected as an SR latch, with SPDT switch:
VCC ──[10kΩ]──┬── S ──[NOR Gate 1]── Q
│ ↑─────|
│ cross-feedback
│ |─────↓
GND ──────────┤── R ──[NOR Gate 2]── Q̄
│
SPDT switch center
(one contact to S, other to R, both with pull-ups to VCC)More precisely:
- SPDT switch: center terminal floats between two positions
- Position 1 (S side): S connects to GND through switch → S = LOW (active-LOW set) Wait — for NOR SR latch, S=1 sets the latch. Let me redo:
Correct NOR SR latch debounce:
- S normally pulled HIGH through 10kΩ to VCC
- R normally pulled HIGH through 10kΩ to VCC
- SPDT switch: center to GND; one throw to S node, other throw to R node
- Switch in position 1: S pulled LOW, R stays HIGH → S = 0, R = 1…
Actually for NOR SR latch (active-HIGH inputs):
- S = 1 SETS the latch (Q → 1)
- R = 1 RESETS the latch (Q → 0)
SPDT debounce with NOR SR latch — standard configuration:
- Switch position 1: S momentarily goes HIGH (through direct connection or 330Ω current-limit resistor from VCC) → Q = 1. Bounces cause S to go LOW and back HIGH, but Q is already 1 and holds.
- Switch position 2: R goes HIGH → Q = 0. Bounces again irrelevant.
Implementation using 74HC02 (quad NOR):
74HC02 pin 2 (1A) → S input
74HC02 pin 3 (1B) → Q̄ feedback from pin 4 (2Y)
74HC02 pin 1 (1Y) → Q output and feedback to pin 5 (2A)
74HC02 pin 5 (2A) → Q feedback
74HC02 pin 6 (2B) → R input
74HC02 pin 4 (2Y) → Q̄ outputResult: Q output is a perfectly clean, bounce-free signal. No matter how many times the mechanical contacts bounce, Q changes state only once — on the first contact — and holds until the switch moves to the other position.
Advantage over RC debounce: RC + Schmitt trigger debounce suppresses bounces by slowing the signal. NAND/NOR SR latch debounce is instantaneous — it responds immediately to the first contact and then ignores all subsequent bounces. For latching switches (SPDT), the SR latch approach is ideal.
Design Example 5: NAND-Only 2-to-4 Decoder
Application: Implement the 2-to-4 line decoder from Article 80 (Design Example 5) using only NAND gates.
From Article 80, the decoder equations are:
Y0 = Ā1·Ā0 (active-HIGH)
Y1 = Ā1·A0
Y2 = A1·Ā0
Y3 = A1·A0With enable input CS̄ (active-LOW chip select — enable when CS̄=0):
Y0 = Ā1·Ā0·CS where CS = ̄(CS̄) = CSbar inverted
Y1 = Ā1·A0·CS
Y2 = A1·Ā0·CS
Y3 = A1·A0·CSHowever, most practical decoders use active-LOW outputs (outputs go LOW when selected). Active-LOW outputs suit directly driving NAND-gate-based circuits and are typical in memory chip-select applications.
Active-LOW output decoder:
Y0̄ = ̄(Ā1·Ā0·CS) = NAND(Ā1, Ā0, CS)
Y1̄ = NAND(Ā1, A0, CS)
Y2̄ = NAND(A1, Ā0, CS)
Y3̄ = NAND(A1, A0, CS)Each output is the direct output of a 3-input NAND gate — no extra inversion needed! The NAND gate naturally provides the active-LOW output.
Gate implementation:
- Gate 1 (NAND as NOT): both inputs = A0 → Ā0
- Gate 2 (NAND as NOT): both inputs = A1 → Ā1
- Gate 3 (NAND, 3-input): inputs CS, Ā1, Ā0 → Y0̄
- Gate 4 (NAND, 3-input): inputs CS, Ā1, A0 → Y1̄
- Gate 5 (NAND, 3-input): inputs CS, A1, Ā0 → Y2̄
- Gate 6 (NAND, 3-input): inputs CS, A1, A0 → Y3̄
Note: CS = ̄(CS̄). If CS̄ is available (active-LOW chip select), use CS̄ directly as a third input to each NAND gate — when CS̄ = 0, it forces the NAND output HIGH (disabled), and when CS̄ = 1… wait, that’s wrong direction.
For active-LOW CS̄ enabling the decoder (decoder active when CS̄ = LOW): NAND(CS̄, …) outputs HIGH (disabled) when CS̄ = 1 — correct, decoder disabled. NAND(CS̄=0, Ā1, Ā0) = NAND(0, …) = 1 — still HIGH regardless of address. Wrong!
Correct approach: Use CS̄ on the NOT gates’ enables or add an inverter:
- Gate 0 (NAND as NOT): both inputs = CS̄ → CS (active-HIGH enable)
- Then Gates 3–6 use CS (active-HIGH) as third input → when CS=1, decoder enabled
Final ICs:
- Two gates from 74HC00 (for Ā0, Ā1 inverters) + one more for CS̄ inverter
- One 74HC10 (triple 3-input NAND) — uses 3 of 3 gates for Y0̄, Y1̄, Y2̄
- Need 4 three-input NAND outputs but 74HC10 only has 3 — need second 74HC10 for Y3̄, or use 74HC00 plus additional NAND.
Alternative: Use 74HC20 (dual 4-input NAND) for two outputs, 74HC10 for two more. Mix and match within the NAND family to fill exactly the gates needed.
This is the practical approach to NAND-only design: work entirely within the 74HC00/74HC10/74HC20/74HC30 family, choosing whichever package provides the right number and type of NAND gates to fill the design with minimal waste.
Real IC: The 74HC139 (dual 2-to-4 decoder) and 74HC138 (3-to-8 decoder) implement exactly this function in a single optimized IC. They use all-NAND internal logic and provide active-LOW outputs — confirming the design approach above.
Common Applications of NAND and NOR in Real Systems
NAND Flash Memory
NAND gates give their name to NAND flash memory — the storage technology in all USB drives, SSDs, SD cards, and phones. Flash memory cells are arranged in series strings like NAND gate pull-down networks, enabling high density storage. The “NAND” in NAND flash refers to this structural similarity to NAND gate topology.
Set-Reset Inputs on Flip-Flops
Virtually all flip-flop ICs include active-LOW asynchronous set and reset inputs (labeled S̄ and R̄ or PRE̅ and CLR̅). These are implemented internally as NAND SR latches that override the clock-controlled behavior. The active-LOW polarity is natural for NAND implementation and is why these pins are active-LOW on almost every flip-flop IC ever made.
Bus Drivers and Tri-State Logic
NAND gates with enable inputs form the basis of bus driver circuits. When enable = LOW, a NAND gate with one enable input passes the inverse of the data; when enable = HIGH, outputs HIGH regardless of data. Three-state (tri-state) bus drivers extend this to include a high-impedance state, enabling multiple devices to share a common bus.
Memory Address Decoding
In microprocessor systems, NAND gates decode address buses to generate chip-select signals for individual memory chips. Each memory chip has an active-LOW chip select input — perfectly matched to NAND gate outputs. A 74HC20 (4-input NAND) can decode a specific 4-bit address pattern by connecting the appropriate address lines (or their complements through inverters) to the four inputs.
Troubleshooting NAND and NOR Circuits
Problem: NAND output stuck HIGH Most likely cause: one or more inputs are floating LOW or have a faulty connection to the driving signal. NAND outputs HIGH whenever any input is LOW — a floating input defaults to an indeterminate low level in CMOS. Check all input connections. Tie unused inputs to VCC (HIGH).
Problem: NOR output stuck LOW Most likely cause: one or more inputs are floating HIGH or stuck HIGH from a driving fault. NOR outputs LOW whenever any input is HIGH. A floating CMOS input often drifts HIGH in the presence of noise. Check input connections. Tie unused NOR inputs to GND (LOW).
Problem: SR latch oscillates instead of holding state The cross-coupling connections are reversed, creating positive feedback at the wrong input. Verify the feedback: NOR gate 1 output must connect to NOR gate 2’s second input, and NOR gate 2 output must connect back to NOR gate 1’s second input. A common wiring error connects both outputs to the same gate or connects output to the wrong input number.
Problem: NAND oscillator frequency drifts Normal — RC NAND oscillators are not temperature-stable. For better stability, use a 74HC132 (Schmitt trigger NAND) instead of 74HC00, ensure power supply is stable and well-decoupled, and use a high-quality capacitor (film or NPO ceramic, not standard disc ceramic). For precision frequency, replace the RC with a crystal.
Problem: Gate output doesn’t match expected truth table Verify power and decoupling (100nF at VCC pin). Check for incorrect pin numbers — 74HC00 and 74HC02 have different pinouts despite same package. Verify logic family compatibility if mixing 3.3V and 5V devices. Use a logic probe or oscilloscope to check input and output levels.
Summary
NAND and NOR gates are universal: any logic function can be implemented using only NAND gates or only NOR gates. NAND universality comes from three equivalences — NAND with tied inputs = NOT, NAND-NAND in series = AND, NAND(NOT A, NOT B) = OR. NOR universality follows the same pattern with AND and OR swapped.
In CMOS technology, NAND gates are faster than NOR gates (NMOS pull-down networks are faster than PMOS pull-up networks), making NAND the preferred choice in standard cell digital design. Sum-of-Products expressions map directly to two-level NAND-NAND circuits; Product-of-Sums maps directly to two-level NOR-NOR. Bubble-pushing (De Morgan’s law applied graphically) reveals paired bubble cancellations that minimize the inverter count when converting AND/OR/NOT designs to all-NAND or all-NOR.
NAND and NOR cross-coupled pairs form SR latches — the simplest memory elements and the foundation of all flip-flops. NAND SR latches have active-LOW inputs; NOR SR latches have active-HIGH inputs. Both provide perfect switch debouncing when connected to SPDT switches.
Standard ICs — 74HC00 (quad 2-input NAND), 74HC10 (triple 3-input), 74HC20 (dual 4-input), 74HC02 (quad 2-input NOR) — provide the building blocks for any all-NAND or all-NOR design. The five design examples demonstrate complete all-NAND implementations of majority voting, oscillators, alarm systems, switch debouncing, and address decoding — all using only NAND and NOR gate ICs.
